MAC7200 datasheet(650/976 Pages) FREESCALE

650 / 976 page

Initialization/Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

572

Freescale Semiconductor

After the last DMA write (TX mode) to the I2C the module will immediately start the next I2C-bus transfer.

The same is true for RX mode. After the DMA read from the IBDR register the module initiates the next

I2C-bus transfer. This results in 2 possible scenarios in the DMA mode exiting scheme.

1. Fast reaction

The DMAEN bit is cleared before the next I2C-bus transfer completes. In this case the module will

raise an interrupt request to the CPU which can be serviced normally.

2. Slow reaction

The DMAEN bit is cleared after the next I2C-bus transfer has already completed. In this case the

module will not raise an interrupt request to the CPU. Instead the TCF bit can be read to determine

that the transfer completed and the module is ready for further transfer.

What is fast/slow reaction?:

The reaction time TR for the system to disable DMAEN after the last DMA controller access to the I

2C is

the time required for one byte transfer over the I2C. For ’fast reaction’ the disabling has to occur before

the 9th bit of the data transfer which is the ACK bit. So the time available is 8 times the SCL period.

TR = 8 x TSCL

Eqn. 29-5

In fast mode, with 400 kbit/s, TSCL is 2.5 us, so TR is 20us.

Depending on the system and DMA controller there are different possibilities for the deassertion of

DMAEN. Three options are:

1. CPU intervention via Interrupt

The DMA controller is programmed to signal an interrupt to the CPU which is then responsible for

the deassertion of DMAEN. This scheme should be supported by most systems but it can result in

a slow reaction time if other, higher priority interrupts interfer. Therfore the interrupt handling

routine can become complicated as it has to check which of the two cases happened (check TCF

bit) and act accordingly. In case of slow reaction you can force an interrupt for the I2C in the

interrupt controller to have the further transfer handled by the normal I2C interrupt routine. Please

note that the use of nested interrupts can still cause potential issues in this scenario, if you happen

to stall the DMA interrupt between the deassertion and the DMAEN bit and the checking of the

TCF bit.

2. DMA channel linking (if supported)

The Transfer Control Descriptor in the DMA controller that performs the data transfer is linked to

another channel that does a write to the I2C IBCR register to disable the DMAEN bit. This is

probably the fastest system solution, but it uses 2 DMA channels. Please note that you have to make

sure on system level that no higher priority DMA requests occur between the two linked TCDs as

those could again create a scenario of slow reaction.

3. DMA scatter/gather process (if supported)

The Transfer Control Descriptor in the DMA controller that performs the data transfer has the

scatter/gather feature activated. This feature will initiate a reload of another TCD from system

RAM after the completion of the first TCD. The new TCD will have its start bit already set and

immediately start the required write to the I2C IBCR register to disable the DMAEN bit. This TCD

also has scatter/gather activated and is programmed to reload the initial TCD upon completion,

MAC7200 Datasheet(PDF) 650 Page - Freescale Semiconductor, Inc

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