MAC7200 datasheet(647/976 Pages) FREESCALE

647 / 976 page

Initialization/Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

569

29.7.2

DMA Application Information

The DMA interface on the I2C is not completely autonomous and requires intervention from the CPU to

start and to terminate the frame transfer. DMA mode is only valid for Master transmit and Master receive

modes. Software must ensure that the DMA enable bit in the control register is not set when the I2C module

is configured in master mode.

The DMA controller must only transfer one byte of data per Tx/Rx request. This is because there is no

FIFO on the I2C block.

The CPU should also keep the I2C interrupt enabled during a DMA transfer to detect the arbitration lost

condition and take action to recover from this situation. The DMAEN bit in the IBCR register works as a

disable for the transfer complete interrupt. This means that during normal transfers (no errors) there will

always be either an interrupt or a request to the DMA controller, dependent on the setting of the DMAEN

bit. All error conditions will trigger an interrupt and require CPU intervention. The address match

condition will not occur in DMA mode as the I2C should never be configured for slave operation.

The following sections detail how to set up a DMA transfer and what intervention is required from the

CPU. It is assumed that the system DMA controller is capable of generating an interrupt after a certain

number of DMA transfers have taken place.

29.7.2.1

DMA Mode, Master Transmit

The following flow diagram details exactly the operation for using a DMA controller to transmit “n” data

bytes to a slave. The first byte (the slave calling address) is always transmitted by the CPU. All subsequent

data bytes (apart from the last data byte) can be transferred by the DMA controller. The last data byte must

be transferred by the CPU.

MAC7200 Datasheet(PDF) 647 Page - Freescale Semiconductor, Inc