MAC7200 datasheet(643/976 Pages) FREESCALE

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Initialization/Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

565

29.7

Initialization/Application Information

29.7.1

I2C Programming Examples

29.7.1.1

Initialization Sequence

Reset will put the I2C Bus Control Register to its default state. Before the interface can be used to transfer

serial data, an initialization procedure must be carried out, as follows:

1. Update the Frequency Divider Register (IBFD) and select the required division ratio to obtain SCL

frequency from system clock.

2. Update the I2C Bus Address Register (IBAD) to define its slave address.

3. Clear the IBDIS bit of the I2C Bus Control Register (IBCR) to enable the I2C interface system.

4. Modify the bits of the I2C Bus Control Register (IBCR) to select Master/Slave mode,

Transmit/Receive mode and interrupt enable or not. Optionally also modify the bits of the I2C Bus

Interrupt Config Register (IBIC) to further refine the interrupt behaviour.

29.7.1.2

Generation of START

After completion of the initialization procedure, serial data can be transmitted by selecting the 'master

transmitter' mode. If the device is connected to a multi-master bus system, the state of the I2C Bus Busy

bit (IBB) must be tested to check whether the serial bus is free.

If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be sent. The data

written to the data register comprises the slave calling address and the LSB, which is set to indicate the

direction of transfer required from the slave.

The bus free time (i.e., the time between a STOP condition and the following START condition) is built

into the hardware that generates the START cycle. Depending on the relative frequencies of the system

clock and the SCL period, it may be necessary to wait until the I2C is busy after writing the calling address

to the IBDR before proceeding with the following instructions. This is illustrated in the following example.

An example of the sequence of events which generates the START signal and transmits the first byte of

data (slave address) is shown below:

while (bit 5, IBSR ==1)// wait in loop for IBB flag to clear

bit4 and bit 5, IBCR = 1// set transmit and master mode, i.e. generate start condition

IBDR = calling_address// send the calling address to the data register

while (bit 5, IBSR ==0)// wait in loop for IBB flag to be set

29.7.1.3

Post-Transfer Software Response

Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte

communication is finished. The I2C Bus interrupt bit (IBIF) is set also; an interrupt will be generated if the

interrupt function is enabled during initialization by setting the IBIE bit. The IBIF (interrupt flag) can be

cleared by writing 1 (in the interrupt service routine, if interrupts are used).

The TCF bit will be cleared to indicate data transfer in progress by reading the IBDR data register in

receive mode or writing the IBDR in transmit mode. The TCF bit should not be used as a data transfer

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