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MAC7200 Datasheet(PDF) 648 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 648 Page - Freescale Semiconductor, Inc |
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648 / 976 page ![]() Initialization/Application Information MAC7200 Microcontroller Family Reference Manual, Rev. 2 570 Freescale Semiconductor Figure 29-16. Flow-Chart of DMA Mode Master Transmit 29.7.2.2 DMA Mode, Master RX The following flow diagram details the exact operation for using a DMA controller to receive “n” data bytes from a slave. The first byte (the slave calling address) is always transmitted by the CPU. All subsequent data bytes (apart from the two last data bytes) can be read by the DMA controller. The last two data bytes must be transferred by the CPU. Config I2C for Master TX CPU writes calling address to slave interrupt generated Arb Lost or No ack ? CPU handles condition yes no CPU sets DMAENABLE DMA writes 1 ipd_rx_req generated DMA written data ? (n-1) bytes of no yes CPU clears DMA enable interrupt generated Start Generated byte of data CPU writes last data byte interrupt generated CPU clears MS/SL bit in CR Stop generated |
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