MAC7200 datasheet(653/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

575

Chapter 30

Deserial Serial Peripheral Interface (DSPI)

30.1

Introduction to the DSPI on MAC7200

The De-serialization Serial Peripheral Interface (DSPI) block provides a synchronous serial bus for

communication between an MCU and an external peripheral device. On the MAC72xx , the DSPIs operate

only in serial peripheral interface (SPI) configuration, where the DSPI operates as a basic SPI or as a

queued SPI through the use of internal FIFOs.

30.2

DSPI Features

•

Full Duplex, Synchronous Transfers.

•

Master or Slave Operation.

•

Programmable Master Bit Rates.

•

Programmable Clock Polarity and Phase.

•

End-of-Transmission Interrupt Flag.

•

Programmable transfer Baud rate.

•

Programmable data frames from 4-bits to 16-bits.

•

Up to 6 chip select lines enable 64 external devices to be selected using external muxing from a

single DSPI.

•

8 Clock and Transfer Attributes registers.

•

Chip Select Strobe available as alternate function on one of the Chip Select pins for de-glitching.

•

Two dedicated DMA request lines on each peripheral for receive and transmit data.

•

FIFO for buffering up to 4 transfers on the transmit and receive side.

•

Queueing operation possible through use of the DMA controllers channels.

•

General purpose I/O functionality on pins when not used for SPI

On the MAC72xx, the de-serialization feature of the DSPI is not available.

30.3

DSPI Protocol

The SPI bus is a 4-wire serial communications interface used for medium speed (less than 100 MB/s). The

interface consists of the following 4 pins:

•

SCK (Serial Data Clock): Data is shifted/latched on the rising or falling edge of SCK, depending

on value of the CPOL control bit. This signal is bussed (i.e., one signal for all Slaves).

•

MOSI (Master Output/Slave Input): Data is transmitted out of this pin if the chip is a Master and

into this pin if the chip is a Slave. This signal is bused (i.e., 1 signal for all Slaves).

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