MAC7200 datasheet(671/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

593

Address: DSPI_BASE + 0x2C

Access:

TCF

TXRXS

EOQF TFUF

TFFF

RFOF

RFDF

Reset

000

TXCTR

TXNXTPTR

RXCTR

POPNXTPTR

Reset

000

Figure 30-6. DSPI Status Register (DSPI_SR)

Table 30-17. DSPI_SR Field Descriptions

Field

Description

TCF

Transfer Complete Flag. The TCF bit indicates that all bits in a frame have been shifted out. The TCF bit

is set at the end of the frame transfer. The TCF bit remains set until cleared by software.

0 Transfer not complete

1Transfer complete

TXRXS

TX & RX Status. The TXRXS bit reflects the status of the DSPI. See Section 30.12.2, “Start and Stop of

DSPI Transfers,” for information on how what causes this bit to be negated or asserted.

0 TX and RX operations are disabled (DSPI is in STOPPED state)

1 TX and RX operations are enabled (DSPI is in RUNNING state)

Reserved, should be cleared.

EOQF

End of Queue Flag. The EOQF bit indicates that transmission in progress is the last entry in a queue. The

EOQF bit is set when TX FIFO entry has the EOQ bit set in the command halfword and the end of the

transfer is reached. The EOQF bit remains set until cleared by software. When the EOQF bit is set, the

TXRXS bit is automatically cleared.

0 EOQ is not set in the executing command

1 EOQ bit is set in the executing SPI command

TFUF

Transmit FIFO Underflow Flag. The TFUF bit indicates that an underflow condition in the TX FIFO has

occurred. The transmit underflow condition is detected only for DSPI blocks operating in slave mode and

SPI configuration. The TFUF bit is set when the TX FIFO of a DSPI operating in SPI slave mode is empty,

and a transfer is initiated by an external SPI master. The TFUF bit remains set until cleared by software.

0 TX FIFO underflow has not occurred

1 TX FIFO underflow has occurred

Reserved, should be cleared.

TFFF

Transmit FIFO Fill Flag. The TFFF bit provides a method for the DSPI to request more entries to be added

to the TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be cleared by host

software or an acknowledgement from the DMA controller when the TX FIFO is full.

0 TX FIFO is full

1 TX FIFO is not full

24–20

Reserved, should be cleared.

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