MAC7200 datasheet(689/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

611

The Master places its second data bit on the SOUT line one system clock after odd numbered SCK edge.

The point where the Master samples the Slave SOUT is selected by writing to the SMPL_PT field in the

DSPI_MCR. The SMPL_PT field description in Table 30-8 lists the number of system clock cycles

between the active edge of SCK and the Master Sample point. The Master sample point can be delayed by

one or two system clock cycles.

Figure 30-18 shows the modified transfer format for CPHA = 0. Only the condition where CPOL = 0 is

illustrated. The delayed Master sample points are indicated with a lighter shaded arrow.

Figure 30-18. DSPI Modified Transfer Format (MTFE=1, CPHA=0, Fsck = Fsys/4)

30.12.5.4 Modified SPI Transfer Format (MTFE = 1, CPHA = 1)

Figure 30-19 shows the Modified Transfer Format for CPHA = 1. Only the condition where CPOL = 0 is

described. At the start of a transfer the DSPI asserts the PCS signal to the slave device. After the PCS to

SCK delay has elapsed the master and the slave put data on their SOUT pins at the first edge of SCK. The

Slave samples the Master SOUT signal on the even numbered edges of SCK. The Master samples the

Slave SOUT signal on the odd numbered SCK edges starting with the 3rd SCK edge. The Slave samples

the last bit on the last edge of the SCK. The Master samples the last Slave SOUT bit one half SCK cycle

after the last edge of SCK. No clock edge will be visible on the Master SCK pin during the sampling of

the last bit. The SCK to PCS delay must be greater or equal to half of the SCK period.

tCSC

SCK

System

Master

Slave

PCS

tCSC = PCS to SCK delay

SOUT

Master

SOUT

Sample

Slave

Sample

Sys

Clock

tASC

Clk

Sys

Clk

tASC = After SCK delay

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