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MAC7200 Datasheet(PDF) 691 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 691 Page - Freescale Semiconductor, Inc |
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691 / 976 page  Functional Description MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 613 Figure 30-20. Example of Non-Continuous Format (CPHA=1, CONT=0) When the CONT bit = 1, the PCS signal remains asserted for the duration of the two transfers. The Delay between Transfers (tDT) is not inserted between the transfers. Figure 30-21 shows the timing diagram for two four-bit transfers with CPHA = 1 and CONT = 1. Figure 30-21. Example of Continuous Transfer (CPHA=1, CONT=1) Switching CTAR registers or changing which PCS signals are asserted between frames while using Continuous Selection can cause errors in the transfer. The PCS signal should be negated before CTAR is switched or different PCS signals are selected. tCSC tDT tCSC SCK PCSx SCK Master SOUT Master SIN tCSC = PCS to SCK delay tDT = Delay after Transfer (minimum CS negation time) (CPOL = 0) (CPOL = 1) tASC tASC = After SCK delay tCSC tCSC SCK PCS SCK Master SOUT Master SIN tCSC = PCS to SCK delay (CPOL = 0) (CPOL = 1) tASC (CPOL = 0) SCK tASC = After SCK delay |
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