MAC7200 datasheet(694/976 Pages) FREESCALE

694 / 976 page

Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

616

Freescale Semiconductor

30.12.7.2 Transmit FIFO Fill Interrupt or DMA Request

The Transmit FIFO Fill Request indicates that the TX FIFO is not full. The Transmit FIFO Fill Request is

generated when the number of entries in the TX FIFO is less than the maximum number of possible entries,

and the TFFF_RE bit in the DSPI_RSER is asserted. The TFFF_DIRS bit in the DSPI_RSER selects

whether a DMA request or an interrupt request is generated.

30.12.7.3 Transfer Complete Interrupt Request

The Transfer Complete Request indicates the end of the transfer of a serial frame. The Transfer Complete

Request is generated at the end of each frame transfer when the TCF_RE bit is set in the DSPI_RSER.

30.12.7.4 Transmit FIFO Underflow Interrupt Request

The Transmit FIFO Underflow Request indicates that an underflow condition in the TX FIFO has

occurred. The transmit underflow condition is detected only for DSPI blocks operating in slave mode and

SPI configuration. The TFUF bit is set when the TX FIFO of a DSPI operating in slave mode and SPI

configuration is empty, and a transfer is initiated from an external SPI master. If the TFUF bit is set while

the TFUF_RE bit in the DSPI_RSER is asserted, an interrupt request is generated.

30.12.7.5 Receive FIFO Drain Interrupt or DMA Request

The Receive FIFO Drain Request indicates that the RX FIFO is not empty. The Receive FIFO Drain

Request is generated when the number of entries in the RX FIFO is not zero, and the RFDF_RE bit in the

DSPI_RSER is asserted. The RFDF_DIRS bit in the DSPI_RSER selects whether a DMA request or an

interrupt request is generated.

30.12.7.6 Receive FIFO Overflow Interrupt Request

The Receive FIFO Overflow Request indicates that an overflow condition in the RX FIFO has occurred.

A Receive FIFO Overflow request is generated when RX FIFO and shift register are full and a transfer is

initiated. The RFOF_RE bit in the DSPI_RSER must be set for the interrupt request to be generated.

Depending on the state of the ROOE bit in the DSPI_MCR, the data from the transfer that generated the

overflow is either ignored or shifted in to the shift register. If the ROOE bit is set, the incoming data is

shifted in to the shift register. If the ROOE bit is negated, the incoming data is ignored.

30.12.8 Power Saving Features

The DSPI supports three power-saving strategies:

•

External Stop Mode

•

Module Disable Mode - Clock gating of non-memory mapped logic

•

Clock gating and clock to memory-mapped logic

The External Stop Mode requires a block external to the DSPI to implement the SoC power management

and clock gating control. All power saving features require logic external to the DSPI. Figure 30-24 shows

an example on how the DSPI power saving features can be used in an SoC.

MAC7200 Datasheet(PDF) 694 Page - Freescale Semiconductor, Inc