Q6000 datasheet(29/98 Pages) INTEL

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Datasheet

Electrical Specifications

Table 19.

FSB Differential Clock Specifications (1333 MHz FSB)

T# Parameter

Min

Nom

Max

Unit

Figure

Notes1

NOTES:

Unless otherwise noted, all specifications in this table apply to all processor core frequencies

based on a 333 MHz BCLK[1:0].

BCLK[1:0] Frequency

331.635

—

333.364

MHz

Duty Cycle (High time/Period) must be between 40 and 60%.

T1: BCLK[1:0] Period

2.99972

—

3.01536

The period specified here is the average period. A given period may vary from this specification

as governed by the period stability specification (T2). Min period specification is based on -300

PPM deviation from a 3 ns period. Max period specification is based on the summation of +300

PPM deviation from a 3 ns period and a +0.5% maximum variance due to spread spectrum

clocking.

T2: BCLK[1:0] Period Stability

—

150

4, 5

For the clock jitter specification, refer to the CK505 Clock Synthesizer/Driver Specification.

In this context, period stability is defined as the worst case timing difference between successive

crossover voltages. In other words, the largest absolute difference between adjacent clock

periods must be less than the period stability.

T5: BCLK[1:0] Rise and Fall Slew Rate

2.5

—

V/nS

Measurement taken from differential waveform.

T6: Slew Rate Matching

N/A

Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured

using a ±75 mV window centered on the average cross point where Clock rising meets Clock#

falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to

use for the edge rate calculations. Slew rate matching is a single ended measurement.

Figure 3.

Differential Clock Waveform

High Time

Period

CROSS

CLK 1

CLK 0

Low Time

VCROSS Min

300 mV

VCROSS Max

500 mV

median

CROSS

median

CROSS

Median + 75 mV

Median - 75 mV

CROSS

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