R261 datasheet(10/28 Pages) ONSEMI

10 / 28 page

BelaSigna R261

http://onsemi.com

Figure 4. Analog Portion of BelaSigna R261 (Bumps facing up)

Analog Ground Plane

Digital Ground Plane

G1 = MIC0

E1 = MIC2

F2 = RESERVED

G3 = VREG

E3 = VMIC

F4 = VSSA

D4 = NRESET

G5 = VDDA

E5 = AI1

F6 = VBAT

D6 = A_OUT0

G7 = CAP0

E7 = A_OUT1

F8 = CAP1

G9 = VBATRCVR

E9 = VSSRCVR

C1 = I2C_SCL

A1 = DEBUG_RX

B2 = DEBUG_TX

C3 = I2C_SDA

A3 = EXT_CLK

B4 = VDDO

C5 = BOOT_SEL

A5 = VSSD

B6 = VDDD

C7 = DMIC_OUT

A7 = SPI_CLK

CONFIG_SEL

B8 = SPI_SERO

ALGO_CTRL

C9 = SPI_SERI

SLEEP_CTRL

A9 = SPI_CS

ATT_SEL

The VSSD plane is used as the ground return for digital

circuits and should be placed under digital circuits. The

VSSA plane should be kept as noise−free as possible. It is

used as the ground return for analog circuits and it should

surround analog components and pins. It should not be

connected to or placed under any noisy circuits such as RF

chips, switching supplies or digital pads of BelaSigna R261

itself. Analog ground returns associated with the audio

output stage should connect back to the star point on separate

individual traces.

For details on which signals require special design

consideration, see Table 4 and Table 5.

In some designs, space constraints may make separate

ground planes impractical. In this case a star configuration

strategy should be used. Each analog ground return should

connect to the star point with separate traces.

Internal Power Supplies

Power management circuitry in BelaSigna R261

generates separate digital (VDDD) and analog (VREG,

VDDA) regulated supplies. Each supply requires an

external decoupling capacitor, even if the supply is not used

externally. Decoupling capacitors should be placed as close

as possible to the power pads.

The digital I/O levels are defined by a separate power

supply pin on BelaSigna R261 (VDDO). This pin must be

externally connected by the application PCB, usually to

VBAT. Note that the voltage on VDDO will influence the

behavior of the LSAD dividers. The system is designed with

the assumption that a 3.3 V power supply voltage is provided

on VBAT, and that VDDO connects to VBAT on the

application PCB.

Further details on these critical signals are provided in

Table 4. Non−critical signals are outlined in Table 5. More

information on the power supply architecture can be found

in the Power Supply Unit section.

R261 Datasheet(PDF) 10 Page - ON Semiconductor

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