R261 datasheet(21/28 Pages) ONSEMI

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BelaSigna R261

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The DMIC host can consequently ignore the algorithm

enable/disable functionality, as both processed and

un−processed signals are always output for all pre−defined

DMIC configurations. This functionality can still be used

with custom DMIC configurations, such as mono. These

custom configurations can be made over the I2C interface.

When the DMIC interface is not required or needed, the

analog outputs can be used for interfacing at line−levels or

other signal levels, e.g. microphone levels for an external

system which expects low level signals (e.g. an analog

baseband chipset).

There are three configurable aspects of the analog output

stage – the selection of stereo (two single ended outputs) or

mono (one differential output), the output attenuation and

the reconstruction filter. When a stereo single−ended option

is selected, each channel is filtered to generate an analog

signal which is then scaled by a configurable output

attenuator (OA in Figure 10). In mono differential mode,

channel 1 is replaced by an inverted version of channel 0

such that the two output pins contain a differential signal for

channel 0. In this latter case, both output attenuators are

used, so it is mandatory to ensure that they have the same

attenuation settings. This can be configured using I2C

commands.

As defined with the CONFIG_SEL pin, some pre−defined

configurations have been designed specifically for use with

analog output instead of DMIC interface. For these

configurations, a differential mono analog output is

pre−configured

the

ROM−based

application.

Consequently, the host processor will have to use the

algorithm enable/disable pin (ALGO_CTRL) or the I2C

interface, to swap between the processed and the

non−processed signal, as shown on Table 12:

Table 12.

ANALOG MONO DIFFERENTIAL OUTPUT SIGNAL

Algorithm Enabled

Algorithm Disabled

A_OUT0 −

A_OUT1

BSE processed signal

Un−processed signal

Alternatively, when stereo analog outputs have been

configured through the I2C interface, the signals on the two

output pins will be as shown on Table 13:

Table 13. ANALOG STEREO OUTPUT SIGNALS

Algorithm Enabled

Algorithm Disabled

A_OUT0

BSE processed signal

Un−processed signal

A_OUT1

Un−processed signal

BSE Processed signal

The attenuation of these analog signals can be done by

using the ATT_SEL mechanism described earlier, but

alternatively, the I2C interface can also be used for this

purpose.

The reconstruction filters can also be altered by I2C

commands; typically, the cut−off frequency can be switched

between 13 kHz (default) and 26 kHz.

The WLCSP-26 package option doesn’t provide access to

the A_OUT0 pin. Consequently, only A_OUT1 is available

as an analog output. For the predefined configurations

(using CONFIG_SEL), the analog output stage is

configured to provide a mono differential output signal, as

described on Table 12. The A_OUT1 signal will thus be an

inverted version of the processed output channel. Access to

the un-processed signal will have to be done with an I2C

command, or potentially with the ALGO_CTRL signal,

with the precautions discussed earlier concerning the

automatic booting process (See the Boot Control section for

additional details).

A third output method is available on BelaSigna R261,

using the Class−D output driver which can drive an output

transducer without the need for a separate power amplifier.

The output driver can also be configured for single ended

stereo or differential mono, through the same I2C commands

as described for the analog outputs.

For optimal audio performance it is important to note that

the VBATRCVR power supply must be connected

differently, depending on whether the output driver or the

analog outputs are being used:

• When using the analog outputs, VBATRCVR must be

connected to VDDA on the application PCB

• When using the output driver, VBATRCVR must be

connected to VBAT on the application PCB and must

be decoupled with an external capacitor

When interfacing BelaSigna R261 with other processors

like codecs or baseband chipsets, it is not recommended to

use the output driver, but rather the analog outputs.

Clock Generation Circuitry

BelaSigna R261 is equipped with a fully configurable and

flexible clocking system, which allows for a large number of

clocking configurations for various different use cases.

Computing applications would typically require the use of

a DMIC interface, which imposes constraints on the

BelaSigna R261 clocking system, such as it provides full

synchronization between an incoming DMIC clock and the

DMIC data that the chip will produce. The input frequencies

that these systems usually operate with are in the range of

2.048 to 3.072 MHz. Mobile phone applications would

typically use much higher clock frequencies; historically,

baseband systems have been using 13 MHz or 26 MHz, or

even 19.2 MHz or 38.4 MHz.

The variety of clocking use cases that BelaSigna R261

must support forced the integration of a phase locked loop

as one of the components of BelaSigna R261’s clock

generation circuitry. This highly configurable PLL is shown

in Figure 12, in the context of the BelaSigna R261 clocking

architecture.

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