R261 datasheet(20/28 Pages) ONSEMI

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BelaSigna R261

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Interpolation

Filter

Output

Driver 0

A_OUT0

A_OUT1

Combiner

DMIC_OUT

From

Application

Channel 0

DAC0

DAC1

From

Application

Channel 1

Digital

Analog

Output Stage Channel 0

Output

Modulator

Interpolation

Filter

Output Stage Channel 1

Output

Modulator

Inversion

Delay,

inversion

and

muxing

Figure 10. Output Stage

OA0

LPF

OA1

LPF

The digital microphone interface provides the PDM

signals directly on a pin (DMIC_OUT), for interfacing with

the DMIC input of external systems. When using this

interface, the EXT_CLK input to BelaSigna R261 must be

given a DMIC_CLK signal and the system’s clocking must

be set up properly, such as proper synchronization can

happen between the incoming DMIC_CLK and the output

data produced by BelaSigna R261 on its DMIC_OUT pin.

Various DMIC_CLK frequencies are supported through

hardware configuration on the CONFIG_SEL pin, as

discussed earlier. Other frequencies could also be supported

under certain conditions, see the clocking section of this

document for more information on the supported DMIC

clock frequencies.

The DMIC output can be configured to carry a mono or

stereo signal. In fact both left and right signals can be

configured to either contain output stage channel 0 or output

stage channel 1. Also, both left and right can be configured

to be muted independently (driving a ‘0’ all the time).

Figure 11 shows the timing of the DMIC output data

relative to the incoming DMIC_CLK signal. See Table 2 for

electrical specifications of the timing parameters.

Figure 11. DMIC Timing Diagram

DMIC_CLK

DMIC_DATA

Left

Data 0

Right

Data 2

DMIC_

HOLD

DMIC_

HOLD

DMIC_

SETUP

DMIC_

SETUP

Right

Data 0

Left

Data 1

Right

Data 1

The ROM−based application pre−configures the DMIC

interface, such as it always outputs a stereo signal with

Channel 0 as the right signal, and Channel 1 as the left signal.

Table 11 shows the actual signals on the right and left

channels of the DMIC interface, depending on the algorithm

enable/disable bit.

Table 11. DMIC OUTPUT SIGNALS

Algorithm Enabled

Algorithm Disabled

Right

BSE processed signal

Un−processed signal

Left

Un−processed signal

BSE Processed signal

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