R261 datasheet(19/28 Pages) ONSEMI

19 / 28 page

BelaSigna R261

http://onsemi.com

configured for bypass or gain values of 12 to 30 dB in 3 dB

steps. The filters can be configured as well; the DC removal

high−pass filter can be bypassed, or set to a cut−off

frequency of 5 Hz, 10 Hz or 20 Hz (default). The low−pass

filter can be either enabled with a 20 kHz cut−off frequency

(default), or bypassed. The lineout selection allows the

preamplifier outputs to be routed back out via the auxiliary

audio input pins. Note that the AI1/LOUT1 pin is not

available on the WLCSP−26 package option.

Two oversampled 16−bit sigma−delta analog−to−digital

converters then convert the analog signals into the digital

domain. The ADCs are running at a sampling rate of 16 kHz

in both Bypass and Active mode. The sampling rate can

potentially be changed using the I2C interface. Changing the

sampling rate in Active mode will cause the noise

cancellation algorithm to stop operating properly, so this

should not be done; however, the sampling rate in Bypass

mode could potentially be changed to other values. Contact

your local technical support for more information.

Input signal amplitudes can also be adjusted in the digital

domain; digital gain for both converted signals can be

adjusted by using I2C commands.

The ROM−based application pre−configures all these

parameters in the input stage such that the algorithm

operates properly. These parameters can be changed using

the I2C interface, but extreme care should be taken when

doing so, as this could alter the performance of the

algorithm.

The AI3 pin is multiplexed with the microphone power

supply. The default mode for the microphone bias is to be

used as a 2 V power supply. Consequently, any application

that plans to use the AI3 input pin or the LOUT0

functionality has to change the VMIC settings to

high-impedance mode, such as the pin can be properly used

as an analog input or a line-out.

Figure 9. Input Stage

ADC0

To IOP

ADC1

Line

out

Decimation

Filter

MIC0

AI1/LOUT1

Line

out

To IOP

Digital

Analog

Input Stage

Channel 0

MIC2

AI3/VMIC/LOUT0

Input Stage

Channel 1

Decimation

Filter

PA0

LPF0

PA1

LPF1

Output Stage

At all times, the application will produce two output

channels. The content of each channel is determined by the

state of the algorithm enable/disable bit, as explained in the

Algorithm Control section. When the algorithm is enabled,

Channel 0 will contain the processed signal and Channel 1

will contain the un−processed signal. Toggling the

algorithm bit will swap these two channels. These two

output channels will then be transmitted to the output stage

hardware block.

Independently from the actual output stage that was

selected, the amplitude of both the processed and the

non−processed channels can be controlled by I2C

commands. A first parameter determines the number of

output shifts (6 dB attenuation or amplification, depending

on the sign) that will be applied to the channels. A second

parameter is a finer mechanism that allows applying a

fractional, broadband gain on the channels. With these two

mechanisms, applied in the digital domain by the application

processor, a great level of flexibility is provided to match the

output level requirements of the target application,

independently for the two output channels. The ROM−based

application has initialized these parameters for proper

operation of the algorithm and correct output levels, so

extreme care should be taken when modifying these

parameters.

The BelaSigna R261 output stage is shown in Figure 10.

The output stage processes the two channels although,

depending on the configuration, one or both of the output

signals are available on the output pins. There are four

options for audio outputs from BelaSigna R261 – a digital

microphone (DMIC) interface, a low−impedance output

driver, a stereo single−ended analog output or a mono

differential analog output. All outputs are generated from a

sigma−delta modulator which produces a pulse density

modulated (PDM) output signal and then provides it to the

appropriate output system, based on the system

configuration.

R261 Datasheet(PDF) 19 Page - ON Semiconductor

R261 Datasheet(HTML) 19 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL