BelaSigna R261

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2

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter

Min

Max

Unit

Power Supply (Applies on VBAT, VBATRCVR and VDDO for “Max” and for

VSSA, VSSRCVR and VSSD for “Min”) (Note 1)

−0.3

4.0

V

Digital input pin voltage

VSSA − 0.3 V

VDDO + 0.3 V

V

Operating temperature range

−40

85

°C

Storage temperature range

−40

85

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. Time limit at maximum voltage must be less than 100 ms.

NOTE: Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

This device series incorporates ESD protection and is tested by the following methods:

− ESD Human Body Model (HBM) tested per AEC−Q100−002 (EIA/JESD22−A114)

− ESD Machine Model (MM) tested per AEC−Q100−003 (EIA/JESD22−A115)

− ESD Charge Discharge Model (CDM) tested per ESD−STM 5−3−1−1999.

This device series incorporates latch−up immunity and is tested in accordance with JESD78:

Electrical Performance Specifications

3.3 V supply voltage (unless noted differently). Parameters marked as screened are tested on each chip. Other parameters are qualified

for all process corners but not tested on every part.)

Parameter

Symbol

Test Conditions / Notes

Min

Typ

Max

Unit

Screened

OVERALL

Supply voltage

VBAT

1.8

3.3

3.63

V

Maximum risetime

VBAT_RISE

Between 0 V and 1.8 V

10

ms

Current consumption

IBAT_ACTIVE Active mode, VBAT = 3.3 V

15

mA

IBAT_BPASS Bypass mode, VBAT = 3.3 V

2.5

3

mA

IBAT3_LOUT Lineout mode, VBAT = 3.3 V

1.2

2

mA

IBAT4_SLEEP Sleep mode, VBAT = 3.3 V

40

mA

VREG (1 mF External Capacitor)

Output voltage

VREG

Without load, or with micro-

phone attached (0 to 200 mA)

0.95

1

1.05

V

PSRR

VREG_PSRR @ 1 kHz

54

dB

Load regulation

VREG_LdReg @ 2 mA

6

mV/mA

Load current

VREG_ILoad

2

mA

Line regulation

VREG_LnReg

0.065

mV/V

VDDA (1 mF External Capacitor on VDDA + 100 nF External Capacitor on CAP0/CAP1)

Output voltage

VDDA

Unloaded with VREG = 1 V

1.8

2

2.1

V

PSRR

VDDA_PSRR @ 1 kHz

45

dB

Load regulation

VDDA_LdReg @ 1 mA, MCLK = 1.28 MHz

110

140

mV/mA

@ 1 mA, MCLK = 2.56 MHz

70

100

mV/mA

Load current

VDDA_ILoad

1

mA

Line regulation

VDDA_LnReg

0.126

mV/V

VDDD (1 mF External Capacitor)

Output voltage

VDDD

1.62

1.8

1.98

V

VMIC

Output voltage

VMIC_VREG VMIC = VREG

0.98

1.0

1.01

V

VMIC_VDDA VMIC = VDDA

1.95

1.98

2.01

V