R261 datasheet(18/28 Pages) ONSEMI

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BelaSigna R261

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The use of a resistive divider, as shown in Figure 8, allows

the application schematic to select the appropriate

combination of clock, output stage and algorithm mode. The

LSAD is using a voltage range between 0 and 1 V. The actual

voltage levels that need to be guaranteed by the application

schematic are also mentioned in Figure 8. The figure

proposes actual resistor values to reach the eight different

presets.

Figure 8. Resistive Dividers for LSAD Preset

Selection

CONFIG_SEL

VREG

Preset

Voltage Range

10 kW

−

0.93 − 1.00 V

16 kW

100 kW

0.79 − 0.91 V

39 kW

100 kW

0.65 − 0.77 V

75 kW

100 kW

0.50 − 0.63 V

100 kW

75 kW

0.36 − 0.49 V

100 kW

39 kW

0.22 − 0.35 V

100 kW

16 kW

0.08 − 0.21 V

−

10 kW

0 − 0.07 V

It is important to note that the configuration is only read

by the chip at boot time, and consequently, it will not be

dynamically updated. So if the voltage on the

CONFIG_SEL is changing during operation, it will only

have an impact at the next reboot operation.

Analog Output Attenuation Control

The hardware configuration method described above,

using an LSAD and a resistive divider is also being used on

another signal called ATT_SEL, such that the application

schematic can select an analog output attenuation to be

applied on the analog output signals. Typically, when

interfacing BelaSigna R261 with a baseband chipset in a cell

phone application, it is very often required to match the

amplitude of the output signals to the input range

requirements of the baseband processor. Table 10 describes

the available values, and their corresponding preset. The

resistive dividers described in Figure 8 can also be used to

configure the ATT_SEL pin.

Table 10. OUTPUT ATTENUATION CONTROL OPTIONS

ATT_SEL: Analog Output

Attenuation Select

Voltage Range

0 (High)

7 (Low)

0.93−1.00

0.79−0.91

0.65−0.77

0.50−0.63

0.36−0.49

0.22−0.35

0.08−0.21

0 − 0.07

Output Attenuation

(Ch0 & Ch1)

0 dB

12 dB

15 dB

18 dB

21 dB

24 dB

27 dB

30 dB

I2C Command Handler

The BelaSigna R261 ROM application contains an I2C

based command and control interface, allowing many

aspects of the chip’s operation and hardware configuration

to be controlled via I2C. This I2C interface is the

recommended way to control the chip and to configure the

application at run−time. The default I2C address of

BelaSigna R261 is 0x61. The I2C interface protocol is fully

supported by the SignaKlara Device Utility (SKDU).

For more information on the I2C interface, please refer to

the I2C interface section of this document, and to the

“BelaSigna R261 Configuration and Communications

Guide.”

System Monitoring

The application software within BelaSigna R261 is

equipped with a few blocks that monitor system sanity. A

watchdog timer is used to ensure proper execution of the

signal processing application. It is always active and is

periodically acknowledged as a check that the application is

still running. Once the watchdog times out, a hardware

system reset will occur. System sanity is also monitored by

the clock detection mechanism; the chip will automatically

enter Sleep mode if it is in Active or Bypass mode and

detects that the external clock source (the signal on

EXT_CLK) is stopped. In this case, the system will only exit

Sleep mode when it detects that the external clock source has

been restored or a reset occurs.

The power supply blocks of the system also monitor for

minimum supply voltages as part of the power supervision

strategy, as described in the Power Management section.

Analog Blocks

Input Stage

The BelaSigna R261 analog audio input stage is shown in

Figure 9. The input stage is comprised of two individual

channels. There are four configurable aspects of each

channel – input multiplexing, preamplifier gain, filtering

and lineout. The input multiplexing allows one input to be

selected from any of the four possible input and then routed

to the inputs of the preamplifier. Each preamplifier can be

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