R261 datasheet(16/28 Pages) ONSEMI

16 / 28 page

BelaSigna R261

http://onsemi.com

putting the system into Sleep mode and waking it up from

Sleep mode cannot be mixed in the same system design.

The first Sleep mode control mechanism is the

SLEEP_CTRL pin. When using SLEEP_CTRL, the

application will transition into or out of Sleep mode

whenever the digital signal transitions to low and stays low

for at least 20 ms, as shown in Figure 7. The actual transition

between modes can occur at any time during the 20 ms low

period of the signal. When SLEEP_CTRL is used to put the

chip into Sleep mode, only another high−to−low transition

on SLEEP_CTRL or a reset will take the system out of Sleep

mode.

The operating mode after exiting Sleep mode using the

SLEEP_CTRL mechanism is always the same as it was

before entering Sleep mode (Active mode in the case of

Figure 7).

SLEEP_CTRL

Operating Mode

20 ms (min)

Active

Sleep

Active

Figure 7. SLEEP_CTRL Timing Example

20 ms (min)

The second method for Sleep mode control is via the I2C

interface. The Switch_Mode command can be used

directly to switch the system into and out of Sleep mode. If

the Switch_Mode command is used to put the chip into

Sleep mode, only another Switch_Mode command or a

reset will take the system out of Sleep mode. When

waking−up by I2C commands, the following I2C operations

have to be performed by the master I2C to ensure proper

wake−up:

1. Send a NOP command to wake up the I2C

interface. This command will not be interpreted by

BelaSigna R261, so the master will have to deal

with any I2C errors that result.

2. Send the Get_Status command in a while−type

loop, until a response from BelaSigna R261 is

sent, and that confirms that the application is in

Standby Mode.

3. Send a Switch_Mode command to enter the

desired mode (Active, Bypass or Line−Out).

When the NOP command is sent and the chip wakes up, the

master has about one second to complete the above

procedure before the chip goes back to Sleep mode. This

mechanism was put in place to deal with I2C bus traffic that

would

wake

the

chip

unintentionally

(i.e.

communications between the master and another slave on

the I2C bus).

The final mechanisms for entering Sleep mode are

considered fail safes to maintain a graceful system shutdown

in the case of invalid operating conditions which could be

that the clock source suddenly stopped. Under this

circumstance, the chip will enter sleep mode to ensure

proper shutdown. More information on this can be found in

the system monitoring section.

The SLEEP_CTRL pin must not be used when the

automatic boot selection method is being used, as described

in Table 9, as BelaSigna R261 will start by searching for an

SPI EEPROM on the multiplexed pins. Consequently, the

SLEEP_CTRL pin must stay unconnected in this mode.

Other mechanisms for controlling sleep mode have to be

used in such cases. This limitation is always there with the

26−ball WLCSP package of BelaSigna R261, since the

BOOT_SEL pin is not available, and hence is always

floating.

Clocking, Output Stage & Algorithm Configuration

As mentioned in the Boot Control section, BelaSigna

R261 can be controlled by hardware configuration when no

EEPROM is present on the application, or when the

BOOT_SEL signal was tied low. The CONFIG_SEL signal

is sampled by BelaSigna R261 during its booting process

using a low−speed A/D converter (LSAD). Based on the

actual voltage that the chip will read on this pin, it will

automatically select a particular clock, output stage and

algorithm configuration, as described in Table 9:

R261 Datasheet(PDF) 16 Page - ON Semiconductor

R261 Datasheet(HTML) 16 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL