R261 datasheet(22/28 Pages) ONSEMI

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BelaSigna R261

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Figure 12. Clocking Circuitry

EXT_CLK

SYS_CLK

Stand−By Clock

PLL Output Clock

External Clock

Activity

Detector

DMIC Sync

MCLK

PLL

/ MCLK_DIV

The ROM−based application has pre−configured the

clocking system in the various hardware presets that are

available, as described in Table 9, but for extended

flexibility, the use of the I2C interface allows changing the

clocking configuration to accommodate specific application

needs.

See

BelaSigna

R261

Configuration

and

Communications Guide for more information.

SYS_CLK is the clock signal that will be used by the

digital signal processing engine inside BelaSigna R261. It

can be either the output of the PLL, as described above or it

can also be driven by the stand−by clock, which is a very low

frequency signal used to minimize power consumption in

Sleep mode. Alternatively, the EXT_CLK signal could also

be used directly by the system, bypassing the internal PLL.

MCLK is the clock signal that is used by the input and

output stages of BelaSigna R261. MCLK must be

configured to stay within the 1.92 MHz – 3.84 MHz range,

to guarantee correct system operation. Among other

parameters, an important impact of the MCLK signal is the

sampling rate.

When the DMIC interface has to be used, BelaSigna R261

automatically synchronizes the EXT_CLK signal and the

MCLK signal, as shown on Figure 12. Since MCLK is used

to generate the DMIC data output, it must be fully

synchronized with the EXT_CLK signal which is the DMIC

clock, such as the DMIC host can properly sample the DMIC

data. Consequently, the range of supported DMIC clock

frequencies is the same as the MCLK range, i.e. 1.92 MHz

to 3.84 MHz.

As discussed in the System Monitoring section,

BelaSigna R261 is equipped with a clock detection

mechanism that will permanently monitor activity on the

EXT_CLK signal. This will ensure that whenever this clock

source disappears, BelaSigna R261 will properly enter a

known state, using an internal clocking signal, until the

external clock comes back.

It has to be noted that the internal PLL of BelaSigna R261

has a free−running mode, whereby it is capable to operate

without an external clock reference to be provided. This

mode requires special configuration, but can be used when

it is not necessary to guarantee an exact clock frequency or

when the sampling rate accuracy isn’t important.

For more information on the configuration of this

clocking

architecture,

refer

BelaSigna

R261

Configuration and Communications Guide.

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