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ADS1294 Datasheet(PDF) 34 Page - Texas Instruments |
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ADS1294 Datasheet(HTML) 34 Page - Texas Instruments |
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34 / 88 page ![]() DRDY DOUT SCLK Bit215 Bit214 Bit213 GPIOPin GPIOData(read) GPIOData(write) GPIOControl ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459H – JANUARY 2010 – REVISED OCTOBER 2011 www.ti.com Figure 38 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an ADS1298 with a selected data rate that gives 24-bit resolution). DOUT is latched out at the rising edge of SCLK. DRDY is pulled high at the falling edge of SCLK. Note that DRDY goes high on the first falling edge SCLK regardless of whether data are being retrieved from the device or a command is being sent through the DIN pin. Figure 38. DRDY with Data Retrieval (CS = 0 in RDATA mode) GPIO The ADS129x have a total of four general-purpose digital I/O (GPIO) pins available in the normal mode of operation. The digital I/O pins are individually configurable as either inputs or as outputs through the GPIOC bits register. The GPIOD bits in the GPIO register control the level of the pins. When reading the GPIOD bits, the data returned are the logic level of the pins, whether they are programmed as inputs or outputs. When the GPIO pin is configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an output, a write to the GPIOD bit sets the output value. If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on or after a reset. Figure 39 shows the GPIO port structure. The pins should be shorted to DGND if not used. GPIO1 can be used as the PACEIN signal; GPIO2 is multiplexed with RESP_BLK signal; GPIO3 is multiplexed with the RESP signal; and GPIO4 is multiplexed with the RESP_PH signal. Figure 39. GPIO Port Pin Power-Down (PWDN) When PWDN is pulled low, all on-chip circuitry is powered down. To exit power-down mode, take the PWDN pin high. Upon exiting from power-down mode, the internal oscillator and the reference require time to wake up. It is recommended that during power-down the external clock is shut down to save power. 34 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R |
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