ADS1294 datasheet(33/88 Pages) TI

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SCLK

DRDY

DOUT

STAT

24-Bit

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

216SCLKs

DIN

ADS1294, ADS1294R

ADS1296, ADS1296R

ADS1298, ADS1298R

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SBAS459H

– JANUARY 2010 – REVISED OCTOBER 2011

Data Output (DOUT)

The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS129x. Data on

DOUT are shifted out on the rising edge of SCLK. DOUT goes to a high-impedance state when CS is high. In

read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line

also indicates when new data are available. This feature can be used to minimize the number of connections

between the device and the system controller.

Figure 37 shows the data output protocol for ADS1298.

Figure 37. SPI Bus Data Output for the ADS1298 (Eight Channels)

Data Retrieval

Data retrieval can be accomplished in one of two methods. The read data continuous command (see the

RDATAC: Read Data Continuous section) can be used to set the device in a mode to read the data continuously

without sending opcodes. The read data command (see the RDATA: Read Data section) can be used to read

just one data output from the device (see the SPI Command Definitions section for more details). The conversion

data are read by shifting the data out on DOUT. The MSB of the data on DOUT is clocked out on the first SCLK

rising edge. DRDY returns to high on the first SCLK falling edge. DIN should remain low for the entire read

operation.

The number of bits in the data output depends on the number of channels and the number of bits per channel.

For the ADS1298/8R, the number of data outputs is (24 status bits + 24 bits

× 8 channels) = 216 bits. The format

of the 24 status bits is: (1100 + LOFF_STATP + LOFF_STATN + bits[4:7] of the GPIO register). The data format

for each channel data are twos complement and MSB first. When channels are powered down using the user

remains the same. For the ADS1294/4R and ADS1296/6R, the last four and two channel outputs shown in

Figure 37 are zeros. The four and six channels parts require only 120 and 168 SCLKs to shift data out,

respectively. Status and GPIO register bits are loaded into the 24-bit status word 2tCLKs before DRDY goes low.

The ADS129x also provide a multiple readback feature. The data can be read out multiple times by simply giving

more SCLKs, in which case the MSB data byte repeats after reading the last byte. The DAISY_EN bit in

CONFIG1 register must be set to '1' for multiple readbacks.

Data Ready (DRDY)

DRDY is an output. When it transitions low, new conversion data are ready. The CS signal has no effect on the

data ready signal. The behavior of DRDY is determined by whether the device is in RDATAC mode or the

RDATA command is being used to read data on demand. (See the RDATAC: Read Data Continuous and

RDATA: Read Data subsections of the SPI Command Definitions section for further details).

When reading data with the RDATA command, the read operation can overlap the occurrence of the next DRDY

without data corruption.

The START pin or the START command is used to place the device either in normal data capture mode or pulse

data capture mode.

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Product Folder Link(s): ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R

ADS1294 Datasheet(PDF) 33 Page - Texas Instruments

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