Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

ADS1294 Datasheet(PDF) 16 Page - Texas Instruments

Click here to check the latest version.
Part # ADS1294
Description  Low-Power, 8-Channel, 24-Bit Analog Front-End for Biopotential Measurements
PDF  88 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS1294 Datasheet(HTML) 16 Page - Texas Instruments

Back Button ADS1294 Datasheet HTML 12Page - Texas Instruments ADS1294 Datasheet HTML 13Page - Texas Instruments ADS1294 Datasheet HTML 14Page - Texas Instruments ADS1294 Datasheet HTML 15Page - Texas Instruments ADS1294 Datasheet HTML 16Page - Texas Instruments ADS1294 Datasheet HTML 17Page - Texas Instruments ADS1294 Datasheet HTML 18Page - Texas Instruments ADS1294 Datasheet HTML 19Page - Texas Instruments ADS1294 Datasheet HTML 20Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 16 / 88 page
background image
1
CS
SCLK
DIN
DOUT
2
3
8
1
2
8
3
t
CSSC
t
DIST
t
DIHD
t
DOHD
t
CSH
t
DOPD
t
SPWH
t
SPWL
t
SCCS
Hi-Z
t
CSDOZ
t
CSDOD
Hi-Z
t
SCLK
t
SDECODE
CLK
t
CLK
D ISY_IN
A
DOUT
SCLK
MSB
D1
t
DISCK2ST
MSB
2
1
3
216
217
218
MSB
D1
LSB
t
DISCK2HT
t
DOPD
Don’tCare
LSB
D1
219
ADS1294, ADS1294R
ADS1296, ADS1296R
ADS1298, ADS1298R
SBAS459H
– JANUARY 2010 – REVISED OCTOBER 2011
www.ti.com
TIMING CHARACTERISTICS
NOTE: SPI settings are CPOL = 0 and CPHA = 1.
Figure 1. Serial Interface Timing
NOTE: Daisy-chain timing shown for eight-channel ADS1298, ADS1298R, and ADS1298I.
Figure 2. Daisy-Chain Interface Timing
Timing Requirements For Figure 1 and Figure 2
Specifications apply from
–40°C to +85°C, unless otherwise noted. Load on DOUT = 20pF || 100kΩ.
2.7V
≤ DVDD ≤ 3.6V
1.65V
≤ DVDD ≤ 2V
PARAMETER
DESCRIPTION
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
tCLK
Master clock period
414
514
414
514
ns
tCSSC
CS low to first SCLK, setup time
6
17
ns
tSCLK
SCLK period
50
66.6
ns
tSPWH, L
SCLK pulse width, high and low
15
25
ns
tDIST
DIN valid to SCLK falling edge: setup time
10
10
ns
tDIHD
Valid DIN after SCLK falling edge: hold time
10
11
ns
tDOHD
SCLK falling edge to invalid DOUT: hold time
10
10
ns
tDOPD
SCLK rising edge to DOUT valid: setup time
17
32
ns
tCSH
CS high pulse
2
2
tCLKs
tCSDOD
CS low to DOUT driven
10
20
ns
tSCCS
Eighth SCLK falling edge to CS high
4
4
tCLKs
tSDECODE
Command decode time
4
4
tCLKs
tCSDOZ
CS high to DOUT Hi-Z
10
20
ns
tDISCK2ST
DAISY_IN valid to SCLK rising edge: setup time
10
10
ns
tDISCK2HT
DAISY_IN valid after SCLK rising edge: hold time
10
10
ns
16
Submit Documentation Feedback
Copyright
© 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com