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ADS1294 Datasheet(PDF) 31 Page - Texas Instruments |
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ADS1294 Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 88 page ![]() ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R www.ti.com SBAS459H – JANUARY 2010 – REVISED OCTOBER 2011 CLOCK The ADS129x provide two different methods for device clocking: internal and external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room temperature. Over the specified temperature range the accuracy varies; see the Electrical Characteristics. Clock selection is controlled by the CLKSEL pin and the CLK_EN register bit. The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG1 register enables and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 7. The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. It is recommended that during power-down the external clock be shut down to save power. Table 7. CLKSEL Pin and CLK_EN Bit CONFIG1.CLK_EN CLKSEL PIN BIT CLOCK SOURCE CLK PIN STATUS 0 X External clock Input: external clock 1 0 Internal clock oscillator 3-state 1 1 Internal clock oscillator Output: internal clock oscillator DATA FORMAT The ADS129x output 24 bits of data per channel in binary twos complement format, MSB first. The LSB has a weight of VREF/(2 23 – 1). A positive full-scale input produces an output code of 7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 8 summarizes the ideal output codes for different input signals. Note that for DR[2:0] = 000 and 001, the device has only 17 and 19 bits of resolution, respectively. The last seven (in 17-bit mode) or five (in 19-bit mode) bits can be ignored. Table 8. Ideal Output Code versus Input Signal(1)(2) INPUT SIGNAL, VIN (AINP – AINN) IDEAL OUTPUT CODE(3) ≥ VREF 7FFFFFh +VREF/(2 23 – 1) 000001h 0 000000h –VREF/(2 23 – 1) FFFFFFh ≤ –VREF (2 23/223 – 1) 800000h (1) Only valid for 24-bit resolution data rates. (2) Assumes gain = 1. (3) Excludes effects of noise, linearity, offset, and gain error. Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Link(s): ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R |
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