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ADS1294 Datasheet(PDF) 14 Page - Texas Instruments |
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ADS1294 Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 88 page  ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459H – JANUARY 2010 – REVISED OCTOBER 2011 www.ti.com PAG PIN ASSIGNMENTS (continued) NAME PIN FUNCTION DESCRIPTION IN2N(1) 13 Analog input Differential analog negative input 2 IN2P(1) 14 Analog input Differential analog positive input 2 IN1N(1) 15 Analog input Differential analog negative input 1 IN1P(1) 16 Analog input Differential analog positive input 1 TESTP_PACE_OUT1(1) 17 Analog input/buffer output Internal test signal/single-ended buffer output based on register settings TESTN_PACE_OUT2(1) 18 Analog input/output Internal test signal/single-ended buffer output based on register settings AVDD 19 Supply Analog supply AVSS 20 Supply Analog ground AVDD 21 Supply Analog supply AVDD 22 Supply Analog supply AVSS 23 Supply Analog ground VREFP 24 Analog input/output Positive reference voltage VREFN 25 Analog input Negative reference voltage VCAP4 26 Analog output Analog bypass capacitor NC 27 — No connection VCAP1 28 — Analog bypass capacitor NC 29 — No connection VCAP2 30 — Analog bypass capacitor RESV1 31 Digital input Reserved for future use; must tie to logic low (DGND). AVSS 32 Supply Analog ground DGND 33 Supply Digital ground DIN 34 Digital input SPI data in PWDN 35 Digital input Power-down; active low RESET 36 Digital input System reset; active low CLK 37 Digital input/output External Master clock input or internal clock output. START 38 Digital input Start conversion CS 39 Digital input SPI chip select; active low SCLK 40 Digital input SPI clock DAISY_IN 41 Digital input Daisy-chain input; if not used, short to DGND. GPIO1 42 Digital input/output General-purpose input/output pin DOUT 43 Digital output SPI data out GPIO2 44 Digital input/output General-purpose input/output pin GPIO3 45 Digital input/output General-purpose input/output pin GPIO4 46 Digital input/output General-purpose input/output pin DRDY 47 Digital output Data ready; active low DVDD 48 Supply Digital power supply DGND 49 Supply Digital ground DVDD 50 Supply Digital power supply DGND 51 Supply Digital ground CLKSEL 52 Digital input Master clock select AVSS1 53 Supply Analog ground AVDD1 54 Supply Analog supply VCAP3 55 Analog Analog bypass capacitor; internally generated AVDD + 1.9V. AVDD 56 Supply Analog supply AVSS 57 Supply Analog ground AVSS 58 Supply Analog ground AVDD 59 Supply Analog supply RLDREF 60 Analog input Right leg drive noninverting input RLDINV 61 Analog input/output Right leg drive inverting input RLDIN(2) 62 Analog input Right leg drive input to MUX (2) Connect unused terminals to AVDD. 14 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R |
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