ADS1294 datasheet(32/88 Pages) TI

32 / 88 page

ADS1294, ADS1294R

ADS1296, ADS1296R

ADS1298, ADS1298R

SBAS459H

– JANUARY 2010 – REVISED OCTOBER 2011

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SPI INTERFACE

The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads

conversion data, reads and writes registers, and controls the ADS129x operation. The DRDY output is used as a

status signal to indicate when data are ready. DRDY goes low when new data are available.

Chip Select (CS)

Chip select (CS) selects the ADS129x devices for SPI communication. While CS is low the serial interface is

active CS must remain low for the entire duration of the serial communication. After the serial communication is

finished, always wait four or more tCLK cycles before taking CS high. When CS is taken high, the serial interface

is reset, SCLK and DIN are ignored, and DOUT enters a high-impedance state. DRDY asserts when data

conversion is complete, regardless of whether CS is high or low.

While ADS129x is selected the device will attempt to decode and execute commands every eight serial clocks. If

the devices ceases to execute serial commands, it is possible extra clock pulses were presented and placed the

serial interface in an unknown state. Take CS high and back low to reset the serial interface to a known state.

Serial Clock (SCLK)

SCLK is the serial peripheral interface (SPI) serial clock. It is used to shift in commands and shift out data from

the device. The serial clock (SCLK) features a Schmitt-triggered input and clocks data on the DIN and DOUT

pins into and out of the ADS129x. Even though the input has hysteresis, it is recommended to keep SCLK as

clean as possible to prevent glitches from accidentally forcing a clock event. The absolute maximum limit for

SCLK is specified in the Serial Interface Timing table.

While ADS129x is selected(CS = LOW), the device attempts to decode and execute commands every eight

serial clocks. It is therefore recommended that multiples of 8 SCLKs be presented every serial transfer to keep

the interface in a normal operating mode. If the interface ceases to function because of extra serial clocks, it can

be reset by toggling CS high and back to low.

For a single device, the minimum speed needed for the SCLK depends on the number of channels, number of

bits of resolution, and output data rate. (For multiple cascaded devices, see the Cascade Mode subsection of the

Multiple Device Configuration section.)

tSCLK < (tDR – 4tCLK)/(NBITS × NCHANNELS + 24)

(6)

For example, if the ADS1298 is used in a 500SPS mode (eight channels, 24-bit resolution), the minimum SCLK

speed is 110kHz.

Data retrieval can be done either by putting the device in RDATAC mode or by issuing a RDATA command for

data on demand. The above SCLK rate limitation applies to RDATAC. For the RDATA command, the limitation

applies if data must be read between two consecutive DRDY signals. The above calculation assumes that there

are no other commands issued between data captures.

Data Input (DIN)

The data input pin (DIN) is used along with SCLK to communicate with the ADS129x (opcode commands and

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Product Folder Link(s): ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R

ADS1294 Datasheet(PDF) 32 Page - Texas Instruments

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