| Electronic Components Datasheet Search |
|
WM8961 Datasheet(PDF) 114 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8961 Datasheet(HTML) 114 Page - Wolfson Microelectronics plc |
|
114 / 116 page ![]() Pre-Production WM8961 w PP, August 2009, Rev 3.1 114 REGISTER SETTING COMMENT 0x0F - write 0x0000 Reset device if required 0x0F - read - Read Chip ID (=0x1801) 0x08 - write 0x01F4 Enable system clocks 0x57 - write 0x0020 Enable the write sequencer. 0x5A - write 0x0080 Start the write sequencer to configure pre-programmed enable of the DAC playback (digital input to headphone output) path. Analogue input PGAs still muted. Allow enough time for the sequencer to finish 0x5D - read - Read status of write sequencer and wait until the WSEQ_BUSY,bit0,=0 which indicates that the DAC playback path has been configured. Then continue. 0x5A - write 0x0092 Start the write sequencer to configure pre-programmed enable of the ADC record (line input to digital output) path Allow enough time for the sequencer to finish 0x5D - read - Read status of write sequencer and wait until the WSEQ_BUSY,bit0,=0. Then continue. 0x00 - write 0x011F Unmute left analogue input, leave input PGA volume gain at default 0dB 0x01 - write 0x011F Unmute right analogue input, leave input PGA volume gain at default 0dB Table 72 Register Settings for LRINPUT to ADC Record |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |