DP83620 datasheet(10/105 Pages) TI

10 / 105 page

DP83620

SNLS339C – JANUARY 2011 – REVISED APRIL 2013

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3.7

JTAG INTERFACE

Signal Name

Pin Name

Type

Pin #

Description

TCK

I, PU

TEST CLOCK

This pin has a weak internal pullup.

TDO

TEST OUTPUT

TMS

I, PU

TEST MODE SELECT

This pin has a weak internal pullup.

TRST#

I, PU

TEST RESET: Active low test reset.

This pin has a weak internal pullup.

TDI

I, PU

TEST DATA INPUT

This pin has a weak internal pullup.

3.8

RESET AND POWER DOWN

Signal Name

Pin Name

Type

Pin #

Description

RESET_N

I, PU

RESET: Active Low input that initializes or re-initializes the DP83620.

Asserting this pin low for at least 1 µs will force a reset process to occur.

All internal registers will re-initialize to their default states as specified for

each bit in the Register Block section. All strap options are re-initialized as

well.

PWRDOWN/INTN

I, PU

The

default

function

this

POWER

DOWN.

POWER DOWN: Asserting this signal low enables the DP83620 Power

Down mode of operation. In this mode, the DP83620 will power down and

consume minimum power. Register access will be available through the

Management

Interface

configure

and

power

the

device.

INTERRUPT: This pin may be programmed as an interrupt output instead

of a Powerdown input. In this mode, Interrupts will be asserted low using

this pin. Register access is required for the pin to be used as an interrupt

mechanism. See Interrupt Mechanisms for more details on the interrupt

mechanisms.

3.9

STRAP OPTIONS

The DP83620 uses many of the functional pins as strap options to place the device into specific modes of

operation. The values of these pins are sampled at power up or hard reset. During software resets, the

strap options are internally reloaded from the values sampled at power up or hard reset. The strap option

pin assignments are defined below. The functional pin name is indicated in parentheses.

A 2.2 k

Ω resistor should be used for pull-down or pull-up to change the default strap option. If the default

option is required, then there is no need for external pull-up or pull down resistors. Since these pins may

have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND.

Signal Name

Pin Name

Type

Pin #

Description

PHYAD0

COL

S, O, PU

PHY ADDRESS [4:0]: The DP83620 provides five PHY address pins,

PHYAD1

RXD_3

S, O, PD

the state of which are latched into the PHYCTRL register at system

PHYAD2

RXD_2

S, O, PD

Hardware-Reset.

PHYAD3

RXD_1

S, O, PD

The DP83620 supports PHY Address strapping values 0 (<00000>)

PHYAD4

RXD_0

S, O, PD

through 31 (<11111>).A PHY Address of 0 puts the part into the MII

Isolate Mode. The MII isolate mode must be selected by strapping

PHY Address 0; changing to Address 0 by register write will not put the

PHY in the MII isolate mode.

PHYAD[0] pin has weak internal pull-up resistor.

PHYAD[4:1] pins have weak internal pull-down resistors.

Pin Descriptions

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