DP83620 datasheet(11/105 Pages) TI

11 / 105 page

DP83620

www.ti.com

SNLS339C – JANUARY 2011 – REVISED APRIL 2013

Signal Name

Pin Name

Type

Pin #

Description

AN_EN

LED_LINK

S, O, PU

AUTO-NEGOTIATION ENABLE: When high, this enables Auto-

AN1

LED_SPEED/FX_S

S, O, PU

Negotiation with the capability set by AN0 and AN1 pins. When low, this

puts the part into Forced Mode with the capability set by AN0 and AN1

AN0

LED_ACT

S, O, PU

pins.

AN0 / AN1: These input pins control the forced or advertised operating

mode of the DP83620 according to the following table. The value on

these pins is set by connecting the input pins to GND (0) or VCC (1)

through 2.2 k

Ω resistors. These pins should NEVER be connected

directly to GND or VCC.

The value set at this input is latched into the DP83620 at Hardware-

Reset.

The float/pull-down status of these pins are latched into the Basic Mode

Control Register and the Auto_Negotiation Advertisement Register

during Hardware-Reset.

The default is 111 since these pins have internal pull-ups.

FIBER MODE DUPLEX SELECTION: If Fiber mode is strapped using

the FX_EN_Z pin (FX_EN_Z = 0), the AN0 strap value is used to select

half or full duplex. AN_EN and AN1 are ignored in Fiber mode since it

is 100 Mb only and does not support Auto-Negotiation. In Fiber mode,

AN1 should not be connected to any system components except the

fiber transceiver.

FX_EN_

AN_EN

AN1

AN0

Forced Mode

10BASE-T, Half-Duplex

10BASE-T, Full-Duplex

100BASE-TX, Half-Duplex

100BASE-TX, Full-Duplex

100BASE-FX, Half-Duplex

100BASE-FX, Full-Duplex

FX_EN_

AN_EN

AN1

AN0

Advertised Mode

10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

100BASE-TX, Full-Duplex

10BASE-T, Half/Full-Duplex,

100BASE-TX, Half/Full-Duplex

CLK_OUT_EN

S, I, PD

CLK_OUT OUTPUT ENABLE: When high, enables clock output on the

CLK_OUT pin at power-up.

FX_EN_Z

RX_ER

S, O, PU

FX ENABLE: This strapping option enables 100Base-FX (Fiber) mode.

This mode is disabled by default. An external pull-down will enable

100Base-FX mode.

LED_CFG

CRS/CRS_DV

S, O, PU

LED CONFIGURATION: This strapping option determines the mode of

operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can

be controlled via the strap option. All modes are configurable via

MII_MODE

RX_DV

S, O, PD

MII MODE SELECT: This strapping option determines the operating

mode of the MAC Data Interface. Default operation is MII Mode with a

value of 0 due to the internal pulldown. Strapping MII_MODE high will

cause the device to be in RMII mode of operation.

MII_MODE

MAC Interface Mode

MII Mode

RMII Mode

PCF_EN

S, I, PD

PHY CONTROL FRAME ENABLE: When high, allows the DP83620 to

respond to PHY Control Frames.

RMII_MAS

TXD_3

S, I, PD

RMII MASTER ENABLE: When MII_MODE is strapped high, this

strapping option enables RMII Master mode, in which the DP83620

uses a 25 MHz crystal connection on X1/X2 and generates the 50 MHz

RMII reference clock. If strapped low when MII_MODE is strapped high,

default RMII operation (RMII Slave) is enabled, in which the DP83620

uses a 50 MHz oscillator input on X1 as the RMII reference clock. This

strap option is ignored if the MII_MODE strap is low.

Pin Descriptions

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