DP83620 datasheet(27/105 Pages) TI

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Data

IDLE

Data

(J/K)

(TR)

T2.26.4

T2.26.1

T2.26.5

T2.26.3

T2.26.2

PMD Input

Pair

CRS/CRS_DV

RXD[1:0]

RX_ER

DP83620

www.ti.com

SNLS339C – JANUARY 2011 – REVISED APRIL 2013

4.30 AC Specifications — RMII Receive Timing (Slave Mode)

Parameter

Description

Notes

Min

Typ

Max

Units

T2.26.1

X1 Clock Period

50 MHz Reference Clock

T2.26.2

RXD[1:0], CRS_DV, and RX_ER

output delay from X1 rising edge(1)

T2.26.3

100BASE-TX mode

18.5

CRS ON delay(2)(3)

bits

100BASE-FX mode

T2.26.4

100BASE-TX mode

CRS OFF delay(4)

bits

100BASE-FX mode

T2.26.5

100BASE-TX mode

RXD[1:0] and RX_ER latency(5)(6)

bits

100BASE-FX mode

(1)

CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. CRS_DV may toggle

synchronously at the end of the packet to indicate CRS de-assertion.

(2)

Per the RMII Specification, output delays assume a 25 pF load.

(3)

CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.

(4)

CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial de-assertion of CRS_DV.

(5)

Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set

to the default value (01).

(6)

Enabling PHY Status Frames will introduce variability in Receive Data Latency due to insertion of PHY Status Frames into the receive

datapath.

Electrical Specifications

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