DP83620 datasheet(28/105 Pages) TI

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RX_CLK

T2.28.1

T2.28.2

T2.28.3

RX_CLK

TX_CLK

CLK_OUT

Data

IDLE

Data

(J/K)

(TR)

T2.27.4

T2.27.1

T2.27.5

T2.27.3

T2.27.2

PMD Input

Pair

RX_DV

CRS/CRS_DV

RXD[1:0]

RX_ER

DP83620

SNLS339C – JANUARY 2011 – REVISED APRIL 2013

www.ti.com

4.31 AC Specifications — RMII Receive Timing (Master Mode)

Parameter

Description

Notes

Min

Typ

Max

Units

T2.27.1

RX_CLK, TX_CLK, CLK_OUT

50 MHz Reference Clock

Clock Period

T2.27.2

RXD[1:0], CRS_DV, RX_DV and

RX_ER output delay from

RX_CLK, TX_CLK, CLK_OUT

rising edge(1)

T2.27.3

100BASE-TX mode

18.5

CRS ON delay(2)(3)

bits

100BASE-FX mode

T2.27.4

100BASE-TX mode

CRS OFF delay(4)

bits

100BASE-FX mode

T2.27.5

100BASE-TX mode

RXD[1:0] and RX_ER latency(5)

bits

100BASE-FX mode

(1)

CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. CRS_DV may toggle

synchronously at the end of the packet to indicate CRS de-assertion.

(2)

Per the RMII Specification, output delays assume a 25 pF load.

(3)

CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.

(4)

CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial de-assertion of CRS_DV.

(5)

Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set

to the default value (01).

4.32 AC Specifications — RX_CLK Timing (RMII Master Mode)

Parameter

Description

Notes

Min

Typ

Max

Units

T2.28.1

RX_CLK High Time

T2.28.2

RX_CLK Low Time

T2.28.3

RX_CLK Period(1)

(1)

The High Time and Low Time will add up to 20 ns.

Electrical Specifications

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