DP83620 datasheet(18/105 Pages) TI

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TX_CLK

TX_EN

TXD[3:0]

PMD Output

Pair

IDLE

DATA

(J/K)

T2.7.1

TX_CLK

TX_EN

TXD[3:0]

PMD Output

Pair

IDLE

DATA

(J/K)

T2.6.1

DP83620

SNLS339C – JANUARY 2011 – REVISED APRIL 2013

www.ti.com

4.10 AC Specifications — 100BASE-TX and 100BASE-FX MII Transmit Packet Latency

Timing

Parameter

Description

Notes

Min

Typ

Max

Units

T2.6.1

TX_CLK to PMD Output Pair

100BASE-TX and 100BASE-FX modes

bits

Latency(1)(2)

(1)

For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of

TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.

(2)

Enabling PHY Control Frames will add latency equal to 8 bits times the PCF_BUF_SIZE setting. For example if PCF_BUF_SIZE is set

to 15, then the additional delay will be 15*8 = 120 bits.

4.11 AC Specifications — 100BASE-TX and 100BASE-FX MII Transmit Packet Deassertion

Timing

Parameter

Description

Notes

Min

Typ

Max

Units

T2.7.1

TX_CLK to PMD Output Pair

100BASE-TX and 100BASE-FX modes

bits

Deassertion(1)

(1)

Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the

first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.

Electrical Specifications

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