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DP83620 Datasheet(PDF) 25 Page - Texas Instruments

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Part # DP83620
Description  Deterministic, Low Transmit and Receive Latency, Selectable Frequency Synchronized Clock Output, Dynamic Link Quality Monitoring
PDF  105 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DP83620 Datasheet(HTML) 25 Page - Texas Instruments

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Symbol
T2.24.1
T2.24.3
T2.24.2
T2.24.4
X1
TXD[1:0]
TX_EN
PMD Output
Pair
Valid data
TX_CLK
TX_EN
TXD[3:0]
CRS/CRS_DV
RX_CLK
RX_DV
RXD[3:0]
T2.23.1
DP83620
www.ti.com
SNLS339C – JANUARY 2011 – REVISED APRIL 2013
4.27 AC Specifications — 10 Mb/s Internal Loopback Timing
Parameter
Description
Notes
Min
Typ
Max
Units
T2.23.1
TX_EN to RX_DV Loopback(1)
10 Mb/s internal loopback mode
2
µs
(1)
Measurement is made from the first falling edge of TX_CLK after assertion of TX_EN.
4.28 AC Specifications — RMII Transmit Timing (Slave Mode)
Parameter
Description
Notes
Min
Typ
Max
Units
T2.24.1
X1 Clock Period
50 MHz Reference Clock
20
ns
T2.24.2
TXD[1:0], TX_EN, Data Setup to X1 rising edge
4
ns
T2.24.3
TXD[1:0], TX_EN, Data Hold from X1 rising edge
2
ns
T2.24.4
X1 Clock to PMD Output Pair Latency (100 Mb)(1)
100BASE-TX or 100BASE-FX
11
bits
(1)
Latency measurement is made from the X1 rising edge to the first bit of symbol.
Copyright © 2011–2013, Texas Instruments Incorporated
Electrical Specifications
25
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