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DP83620 Datasheet(PDF) 16 Page - Texas Instruments

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Part # DP83620
Description  Deterministic, Low Transmit and Receive Latency, Selectable Frequency Synchronized Clock Output, Dynamic Link Quality Monitoring
PDF  105 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DP83620 Datasheet(HTML) 16 Page - Texas Instruments

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T2.2.4
T2.2.2
32 CLOCKS
T2.2.3
output
input
Vcc
X1 clock
Hardware
RESET_N
MDC
Latch-In of Hardware
Configuration Pins
Dual Function Pins
Become Enabled As Outputs
T2.2.1
DP83620
SNLS339C – JANUARY 2011 – REVISED APRIL 2013
www.ti.com
4.6
AC Specifications — Reset Timing
Parameter
Description
Notes
Min
Typ
Max
Units
T2.2.1
Post RESET Stabilization time prior to
MDIO is pulled high for 32-bit serial
3
µs
MDC preamble for register accesses
management initialization
T2.2.2
Hardware Configuration Latch-in Time
Hardware Configuration Pins are
from the Deassertion of RESET (either
described in the Pin Description
3
µs
soft or hard)(1)
section
T2.2.3
Hardware Configuration pins transition
50
ns
to output drivers(1)
T2.2.4
X1 Clock must be stable for at min.
RESET pulse width
of 1 µs during RESET pulse low
1
µs
time.
(1)
It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide fast RC time
constants in order to latch-in the proper value prior to the pin transitioning to an output driver.
16
Electrical Specifications
Copyright © 2011–2013, Texas Instruments Incorporated
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