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DP83620 Datasheet(PDF) 17 Page - Texas Instruments

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Part # DP83620
Description  Deterministic, Low Transmit and Receive Latency, Selectable Frequency Synchronized Clock Output, Dynamic Link Quality Monitoring
PDF  105 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DP83620 Datasheet(HTML) 17 Page - Texas Instruments

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Valid Data
T2.5.1
T2.5.1
T2.5.2
RX_CLK
RXD[3:0]
RX_DV
RX_ER
TX_CL
K
TXD[3:0
]
Valid Data
T2.4.2
T2.4.3
TX_EN
T2.4.1
T2.4.1
MDC
MDIO (output)
MDC
MDIO (input)
T2.3.4
T2.3.1
Valid Data
T2.3.2
T2.3.3
DP83620
www.ti.com
SNLS339C – JANUARY 2011 – REVISED APRIL 2013
4.7
AC Specifications — MII Serial Management Timing
Parameter
Description
Notes
Min
Typ
Max
Units
T2.3.1
MDC to MDIO (Output) Delay Time
0
20
ns
T2.3.2
MDIO (Input) to MDC Setup Time
10
ns
T2.3.3
MDIO (Input) to MDC Hold Time
10
ns
T2.3.4
MDC Frequency
2.5
25
MHz
4.8
AC Specifications — 100 Mb/s MII Transmit Timing
Parameter
Description
Notes
Min
Typ
Max
Units
T2.4.1
TX_CLK High/Low Time
100 Mb/s Normal mode
16
20
24
ns
T2.4.2
TXD[3:0], TX_EN Data Setup to
100 Mb/s Normal mode
10
ns
TX_CLK
T2.4.3
TXD[3:0], TX_EN Data Hold from
100 Mb/s Normal mode
0
ns
TX_CLK
4.9
AC Specifications — 100 Mb/s MII Receive Timing
Parameter
Description
Notes
Min
Typ
Max
Units
T2.5.1
RX_CLK High/Low Time(1)
100 Mb/s Normal mode
16
20
24
ns
T2.5.2
RX_CLK to RXD[3:0], RX_DV, RX_ER
100 Mb/s Normal mode
10
30
ns
Delay
(1)
RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high
and low times will not be violated
Copyright © 2011–2013, Texas Instruments Incorporated
Electrical Specifications
17
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Product Folder Links: DP83620



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