LPC4370 datasheet(107/150 Pages) NXP

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LPC4370

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Product data sheet

Rev. 2 — 21 October 2013

107 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

11.6 I2C-bus

[1]

Parameters are valid over operating temperature range unless otherwise specified. See the I2C-bus specification UM10204 for details.

[2]

tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[3]

A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[4]

Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.

[5]

The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified tf.

[6]

In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

[7]

The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or

tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If

the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[8]

tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the

acknowledge.

[9]

A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the

Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

Table 19.

Dynamic characteristic: I2C-bus pins

Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V.[1]

Symbol

Parameter

Conditions

Min

Max

Unit

fSCL

SCL clock frequency

Standard-mode

100

kHz

Fast-mode

400

kHz

Fast-mode Plus

MHz

fall time

[3][4][5][6]

of both SDA and

SCL signals

Standard-mode

300

Fast-mode

20 + 0.1

 C

300

Fast-mode Plus

120

tLOW

LOW period of the SCL clock

Standard-mode

4.7

s

Fast-mode

1.3

s

Fast-mode Plus

0.5

s

tHIGH

HIGH period of the SCL clock

Standard-mode

4.0

s

Fast-mode

0.6

s

Fast-mode Plus

0.26

s

tHD;DAT

data hold time

[2][3][7]

Standard-mode

s

Fast-mode

s

Fast-mode Plus

s

tSU;DAT

data set-up time

[8][9]

Standard-mode

250

Fast-mode

100

Fast-mode Plus

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