LPC4370 datasheet(108/150 Pages) NXP

108 / 150 page

LPC4370

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 21 October 2013

108 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

11.7 I2S-bus interface

[1]

Clock to the I2S-bus interface BASE_APB1_CLK = 150 MHz; peripheral clock to the I2S-bus interface

PCLK = BASE_APB1_CLK / 12. I2S clock cycle time Tcy(clk) = 79.2 ns; corresponds to the SCK signal in the

I2S-bus specification.

Fig 24. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

tHD;DAT

SCL

1 / fSCL

70 %

30 %

70 %

30 %

tVD;DAT

tHIGH

tLOW

tSU;DAT

Table 20.

Dynamic characteristics: I2S-bus interface pins

Tamb =25 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Conditions and data

refer to I2S0 and I2S1 pins. Simulated values.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

common to input and output

rise time

fall time

tWH

pulse width HIGH

on pins I2Sx_TX_SCK

and I2Sx_RX_SCK

tWL

pulse width LOW

on pins I2Sx_TX_SCK

and I2Sx_RX_SCK

output

tv(Q)

data output valid time on pin I2Sx_TX_SDA

[1]

-4.4

on pin I2Sx_TX_WS

4.3

input

tsu(D)

data input set-up time on pin I2Sx_RX_SDA

[1]

-0

on pin I2Sx_RX_WS

0.20

th(D)

data input hold time

on pin I2Sx_RX_SDA

[1]

-3.7

on pin I2Sx_RX_WS

3.9

LPC4370 Datasheet(PDF) 108 Page - NXP Semiconductors

LPC4370 Datasheet(HTML) 108 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL