LPC4370 datasheet(110/150 Pages) NXP

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LPC4370

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Product data sheet

Rev. 2 — 21 October 2013

110 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

11.9 SSP interface

[1]

Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0

[2]

Tcy(clk) = 12  Tcy(PCLK).

Table 22.

Dynamic characteristics: SSP pins in SPI mode

Tamb =25 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Simulated values.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Tcy(clk)

clock cycle time

full-duplex mode

[1]

-40

when only

transmitting

-20

SSP master

tDS

data set-up time

in SPI mode

13.3

tDH

data hold time

in SPI mode

3.5

tv(Q)

data output valid time

in SPI mode

6.0

th(Q)

data output hold time

in SPI mode

SSP slave

Tcy(PCLK) PCLK cycle time

Tcy(clk)

clock cycle time

[2]

120

tDS

data set-up time

in SPI mode

10.5

tDH

data hold time

in SPI mode

tv(Q)

data output valid time

in SPI mode

4.0

th(Q)

data output hold time

in SPI mode

0.2

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