LPC4370 datasheet(113/150 Pages) NXP

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LPC4370

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Product data sheet

Rev. 2 — 21 October 2013

113 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

11.12 SPIFI

11.13 SGPIO timing

The following considerations apply to SGPIO timing:

• SGPIO input signals are synchronized by the internal clock SGPIO_CLOCK. To

guarantee that no samples are missed, all input signals should have a duration of at

least one SGPIO_CLOCK cycle plus the set-up and hold times.

• When an external clock input is used to generate output data, synchronization causes

a latency of at least one SGPIO_CLOCK cycle. The maximum output data rate is one

output every two SGPIO_CLOCK cycles.

• Synchronization also causes a latency of one SGPIO_CLOCK cycle when sampling

several inputs. This may cause inputs with very similar timings to be sampled with a

difference of one SGPIO_CLOCK cycle.

Table 24.

Dynamic characteristics: SPIFI

Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. CL = 10 pF. Simulated

values.

Symbol

Parameter

Min

Max

Unit

Tcy(clk)

clock cycle time

9.6

tDS

data set-up time

3.4

tDH

data hold time



-ns

tv(Q)

data output valid time

th(Q)

data output hold time

Fig 29. SPIFI timing

SPIFI_SCK

SPIFI data out

SPIFI data in

Tcy(clk)

tDS

tDH

tv(Q)

DATA VALID

th(Q)

DATA VALID

002aah409

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