LPC4370 datasheet(116/150 Pages) NXP

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LPC4370

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Product data sheet

Rev. 2 — 21 October 2013

116 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

[1]

Parameters specified for 40 % of VDD(IO) for rising edges and 60 % of VDD(IO) for falling edges.

[2]

Tcy(clk) = 1/CCLK (see LPC43xx User manual).

[3]

End Of Read (EOR): longest of tCSHOEH, tOEHANV, tCSHBLSH.

[4]

Start Of Read (SOR): longest of tCSLAV, tCSLOEL, tCSLBLSL.

[5]

End Of Write (EOW): earliest of address not valid or EMC_BLSn HIGH.

tBLSHEOW

BLS HIGH to end of write

time

PB = 0

[2]

[5]

1.9 + T

cy(clk)

0.5 + T

cy(clk)

tBLSHDNV

BLS HIGH to data invalid

time

PB = 0

[2]

2.5 + T

cy(clk)

1.4 + Tcy(clk)

tCSHEOW

CS HIGH to end of write

time

[5]

2.0

tBLSHDNV

BLS HIGH to data invalid

time

PB = 1

2.5

1.4

tWEHANV

WE HIGH to address invalid

time

PB = 1

0.9 + T

cy(clk)

2.4 + Tcy(clk)

Table 26.

Dynamic characteristics: Static asynchronous external memory interface …continued

CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V;

2.7 V

 V

DD(IO)  3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles. In a

normal read operation, the EMC changes the address while CS is asserted which results in multiple memory accesses.

Symbol

Parameter[1]

Conditions

Min

Typ

Max

Unit

Fig 31. External static memory read/write access (PB = 0)

tCSLDV

tCSLBLSL

tCSHEOW

tBLSHEOW

tCSLAV

EOR

SOR

EOW

EMC_An

EMC_CSn

EMC_OE

EMC_BLSn

EMC_WE

EMC_Dn

002aag699

tCSHOEH

tOEHANV

tCSHEOR

tam

tCSLSOR

tOELOEH

tCSLOEL

tCSLAV

th(D)

tBLSLBLSH

tBLSHDNV

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