LPC4370 datasheet(118/150 Pages) NXP

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LPC4370

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Product data sheet

Rev. 2 — 21 October 2013

118 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

[1]

Program the EMC_CLKn delay values in the EMCDELAYCLK register (see the LPC43xx User manual).

The delay values must be the same for all SDRAM clocks EMC_CLKn: CLK0_DELAY = CLK1_DELAY =

CLK2_DELAY = CLK3_DELAY.

Table 27.

Dynamic characteristics: Dynamic external memory interface

Simulated data over temperature and process range; CL = 10 pF for EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE,

EMC_An; CL = 9 pF for EMC_Dn; CL = 5 pF for EMC_DQMOUTn, EMC_CLKn, EMC_CKEOUTn; Tamb = 40 C to 85 C;

2.2 V

 V

DD(REG)(3V3)  3.6 V; VDD(IO) =3.3 V  10 %; RD = 1 (see LPC43xx User manual); EMC_CLKn delays CLK0_DELAY

= CLK1_DELAY = CLK2_DELAY = CLK3_DELAY = 0.

Symbol

Parameter

Min

Typ

Max

Unit

Tcy(clk)

clock cycle time

8.4

Common to read and write cycles

td(DYCSV)

DYCS delay time

3.1 + 0.5

 T

cy(clk)

5.1 + 0.5

 T

cy(clk)

th(DYCS)

DYCS hold time

0.3 + 0.5

 T

cy(clk)

0.9 + 0.5

 T

cy(clk)

-ns

td(RASV)

row address strobe valid delay time

3.1 + 0.5

 T

cy(clk)

4.9 + 0.5

 T

cy(clk)

th(RAS)

row address strobe hold time

0.5 + 0.5

 T

cy(clk)

1.1 + 0.5

 T

cy(clk)

-ns

td(CASV)

column address strobe valid delay time

2.9 + 0.5

 T

cy(clk)

4.6 + 0.5

 T

cy(clk)

th(CAS)

column address strobe hold time

0.3 + 0.5

 T

cy(clk)

0.9 + 0.5

 T

cy(clk)

-ns

td(WEV)

WE valid delay time

3.2 + 0.5

 T

cy(clk)

5.9 + 0.5

 T

cy(clk)

th(WE)

WE hold time

1.3 + 0.5

 T

cy(clk)

1.4 + 0.5

 T

cy(clk)

-ns

td(DQMOUTV)

DQMOUT valid delay time

3.1 + 0.5

 T

cy(clk)

5.0 + 0.5

 T

cy(clk)

th(DQMOUT)

DQMOUT hold time

0.2 + 0.5

 T

cy(clk)

0.8 + 0.5

 T

cy(clk)

-ns

td(AV)

address valid delay time

3.8 + 0.5

 T

cy(clk)

6.3 + 0.5

 T

cy(clk)

th(A)

address hold time

0.3 + 0.5

 T

cy(clk)

0.9 + 0.5

 T

cy(clk)

-ns

td(CKEOUTV)

CKEOUT valid delay time

3.1 + 0.5

 T

cy(clk)

5.1 + 0.5

 T

cy(clk)

th(CKEOUT)

CKEOUT hold time

0.5

 T

cy(clk)

0.7 + 0.5

 T

cy(clk)

-ns

Read cycle parameters

tsu(D)

data input set-up time

1.5

0.5

th(D)

data input hold time

0.8

2.2

Write cycle parameters

td(QV)

data output valid delay time

3.8 + 0.5

 T

cy(clk)

6.2 + 0.5

 T

cy(clk)

th(Q)

data output hold time

0.5

 T

cy(clk)

0.7 + 0.5

 T

cy(clk)

-ns

Table 28.

Dynamic characteristics: Dynamic external memory interface; EMC_CLK[3:0]

delay values

Tamb = 40 C to 85 C; VDD(IO) =3.3 V  10 %; 2.2 V  VDD(REG)(3V3)  3.6 V.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

delay time

delay value

CLKn_DELAY = 0

[1]

0.0

CLKn_DELAY = 1 [1]

0.4

0.5

0.8

CLKn_DELAY = 2 [1]

0.7

1.0

1.7

CLKn_DELAY = 3 [1]

1.1

1.6

2.5

CLKn_DELAY = 4 [1]

1.4

2.0

3.3

CLKn_DELAY = 5 [1]

1.7

2.6

4.1

CLKn_DELAY = 6 [1]

2.1

3.1

4.9

CLKn_DELAY = 7 [1]

2.5

3.6

5.8

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