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LPC4370 Datasheet(PDF) 115 Page - NXP Semiconductors |
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LPC4370 Datasheet(HTML) 115 Page - NXP Semiconductors |
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115 / 150 page  LPC4370 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 2 — 21 October 2013 115 of 150 NXP Semiconductors LPC4370 32-bit ARM Cortex-M4/M0 microcontroller 11.14 External memory interface Table 26. Dynamic characteristics: Static asynchronous external memory interface CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 85 C; 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V V DD(IO) 3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles. In a normal read operation, the EMC changes the address while CS is asserted which results in multiple memory accesses. Symbol Parameter[1] Conditions Min Typ Max Unit Read cycle parameters tCSLAV CS LOW to address valid time 3.1 - 1.6 ns tCSLOEL CS LOW to OE LOW time [2] 0.6 + T cy(clk) WAITOEN - 1.3 + Tcy(clk) WAITOEN ns tCSLBLSL CS LOW to BLS LOW time PB = 1 0.7 - 1.8 ns tOELOEH OE LOW to OE HIGH time [2] 0.6 + (WAITRD WAITOEN + 1) Tcy(clk) - 0.4 + (WAITRD WAITOEN + 1) Tcy(clk) ns tam memory access time - - 16 + (WAITRD WAITOEN +1) Tcy(clk) ns th(D) data input hold time 16 - - ns tCSHBLSH CS HIGH to BLS HIGH time PB = 1 0.4 - 1.9 ns tCSHOEH CS HIGH to OE HIGH time 0.4 - 1.4 ns tOEHANV OE HIGH to address invalid PB = 1 2.0 - 2.6 ns tCSHEOR CS HIGH to end of read time [3] 2.0 - 0 ns tCSLSOR CS LOW to start of read time [4] 0- 1.8 ns Write cycle parameters tCSLAV CS LOW to address valid time 3.1 - 1.6 ns tCSLDV CS LOW to data valid time 3.1 - 1.5 ns tCSLWEL CS LOW to WE LOW time PB = 1 1.5 - 0.2 ns tCSLBLSL CS LOW to BLS LOW time PB = 1 0.7 - 1.8 ns tWELWEH WE LOW to WE HIGH time PB = 1 [2] 0.6 + (WAITWR WAITWEN + 1) Tcy(clk) - 0.4 + (WAITWR WAITWEN + 1) Tcy(clk) ns tWEHDNV WE HIGH to data invalid time PB = 1 [2] 0.9 + T cy(clk) - 2.3 + Tcy(clk) ns tWEHEOW WE HIGH to end of write time PB = 1 [2] [5] 0.4 + T cy(clk) - 0.3 + T cy(clk) ns tCSLBLSL CS LOW to BLS LOW PB = 0 0.7 - 1.8 ns tBLSLBLSH BLS LOW to BLS HIGH time PB = 0 [2] 0.9 + (WAITWR WAITWEN + 1) Tcy(clk) - 0.1 + (WAITWR WAITWEN + 1) Tcy(clk) ns |
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