LPC4370 datasheet(145/150 Pages) NXP

145 / 150 page

LPC4370

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 21 October 2013

145 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

18. Revision history

Table 44.

Revision history

Document ID

Release date Data sheet status

Change notice

Supersedes

LPC4370 v.2

20131021

Product data sheet

LPC4371_70 v.1.1

Modifications:

• Part LPC4371 removed.

• LCD added to part LPC4370.

• Data sheet title changed to LPC4370.

• VADC renamed to ADCHS throughout the document. Pin VADC_NEG renamed to

ADCHS_NEG.

• OTP memory size available for general-purpose use corrected.

• SD/MMC timing parameters corrected. See Table 32.

• Band gap characteristics removed.

• Description of RESET pin updated in Table 3.

• Table note 9 added in Table 10.

• Minimum value of parameter VDC changed to 0.1 V. See Table 34 “12-bit ADC

characteristics”.

• Section 13.8 “12-bit ADCHS input selection” added.

• Table 12 “Peripheral power consumption 12-bit ADCHS” added.

• Data sheet status changed to Product data sheet.

LPC4371_70 v.1.1

02112013

Objective data sheet

LPC4371_70 v.1

Modifications:

• SSP0 boot pin functions corrected in Table 5 and Table 4. Pin P3_3 = SSP0_SCK, pin

P3_6 = SSP0_SSEL, pin P3_7 = SSP0_MISO, pin P3_8 = SSP0_MOSI.

• Section 13.7 “Minimizing interference between digital signals and 12-bit ADC signals”

added. Pin description table updated with Table note 13.

• TFBGA100 package added.

• Table 7 “Limiting values” updated.

• Parameter name IDD(ADC) changed to IDDA in Table 10.

• Minimum value for parameter VIL changed to 0 V in Table 10.

• Added note to limit data in Table 25 “Dynamic characteristics: Static asynchronous

external memory interface” to single memory accesses.

• Table 23 “Dynamic characteristics: SPIFI” added.

• Power consumption in active mode corrected. See parameter IDD(REG)(3V3) in Table 10

and graphs Figure 8, Figure 9, and Figure 10.

• Band gap characteristics added. See Table 13 and Figure 17.

• Value of parameter IDD(REG)(3V3) in deep power-down increased to 0.03 μA in

Table 10.

• Value of parameter IDD(IO) in deep power-down increased to 0.05 μA in Table 10.

• Figure 4 “AHB multilayer matrix master and slave connections” updated.

LPC4370 Datasheet(PDF) 145 Page - NXP Semiconductors

LPC4370 Datasheet(HTML) 145 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL