AD9863

Rev. A | Page 35 of 40

Read Operations

The readback of registers can be a single or dual data byte

operation. The readback can be configured to use 3-wire or

4-wire and can be formatted with MSB first or LSB first. The

instruction header is written to the device either MSB or LSB

first (depending on the mode) followed by the 8-bit output data,

appropriately MSB or LSB justified. By default, the output data

is sent to the dedicated output pin (SDO). Three-wire operation

can be configured by setting the SDIO BiDir register. In 3-wire

mode, the SDIO pin will become an output pin after receiving

the 8-bit instruction header with a readback request.

Figure 55 shows 4-wire SPI read with MSB first; Figure 56

shows 3-wire read with MSB first; and Figure 57 shows 4-wire

read with LSB first.

SEN

SCLK

SDIO

SDO

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DON'T CARE

DON'T CARE

DON'T CARE

DON'T CARE

DON'T CARE

INSTRUCTION HEADER

OUTPUT REGISTER DATA

A5

D7

D6

D5

D4

D3

D2

D1

D0

A4

A3

A2

A1

A0

R/W

2/1

Figure 55. 1-Byte Serial Register Readback in MSB First Mode, SDIO BiDir Bit Set Logic Low (Default, 4-Wire Mode)

SEN

SCLK

SDIO

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DON'T CARE

DON'T CARE

A5

A4

A3

A2

A1

A0

R/W

2/1

DON'T CARE

D7

D6

D5

D4

D3

D2

D1

D0

OUTPUT REGISTER DATA

INSTRUCTION HEADER

Figure 56. 1-Byte Serial Register Readback in MSB First Mode, SDIO BiDir Bit Set Logic High (Default, 3-Wire Mode)

SEN

SCLK

SDIO

SDO

DON'T CARE

DON'T CARE

DON'T CARE

A0

A1

A2

A3

A4

A5

R/W

2/1

DON'T CARE

DON'T CARE

DON'T CARE

D0

D1

D2

D3

D4

D5

D6

D7

OUTPUT REGISTER DATA

INSTRUCTION HEADER

Figure 57. 1-Byte Serial Register Readback in LSB First Mode, SDIO BiDir Bit Set Logic Low (Default, 4-Wire Mode)