AD9863 datasheet(25/40 Pages) AD

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AD9863

Rev. A | Page 25 of 40

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Buffered Tx clock output (from IFACE3 pin) equals 2× the

DAC update rate; one rising edge per interleaved Tx sample.

Note the following about the Rx path in FD mode:

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ADC CLK Div register can be used to divide down the

clock driving the ADC, which accepts up to 50 MHz.

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Max ADC sampling rate = 50 MSPS.

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The Rx path output data rate is 2× the ADC sample rate

(interleaved).

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Rx_A output when IFACE2 logic level = low.

Rx_B output when IFACE2 logic level = high.

HD12 Mode

The half-duplex, 12-bit interleaved output mode, HD12, can be

configured using mode pins or the SPI.

HD12 mode supports half-duplex only operations and can

interface to a single 12-bit data bus with independent Rx and Tx

synchronization pins (RxSYNC and TxSYNC). Both the U12

and L12 buses are used on the AD9863, but the logic level of the

Tx/Rx selector (controlled through IFACE1 pin) is used to

disable and three-state the unused bus, allowing U12 and L12 to

be tied together. The MSB of the unused bus acts as the RxSYNC

(during Rx operation) or TxSYNC (during Tx operation). A

single pin is used to output the clocks for Rx and Tx data

latching (from the IFACE3 pin) switching, depending on which

path is enabled. HD12 mode requires interpolation of 2× or 4×.

The following notes provide a general description of the HD12

mode configuration. For more information, refer to Table 15.

Note the following about the Tx path in HD12 mode:

•

Interpolation rate of 2× or 4× can be programmed with

mode pins or SPI.

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Interleaved Tx data accepted on U12 bus, L12 bus MSB

acts as TxSYNC.

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Max DAC update rate = 200 MSPS.

Max Tx input data rate = 80 MSPS/channel (160 MSPS

interleaved).

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TxSYNC is used to direct Tx input data.

TxSYNC = high indicates channel Tx_A data.

TxSYNC = low indicates channel Tx_B data.

Note the following about the Rx path in HD12 mode:

•

ADC CLK Div register can be used to divide down the

clock driving the ADC, which accepts up to 50 MHz.

•

Max ADC sampling rate = 50 MSPS.

•

Output data rate = 2× ADC sample rate.

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Interleaved Rx data output from L12 bus.

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Rx_A output when IFACE2 (or RxSYNC) logic level = low.

Rx_B output when IFACE2 (or RxSYNC) logic level = high.

HD24 Mode

The half-duplex, 24-bit parallel output mode, HD24, can be

configured using mode pins or through SPI programming.

HD24 mode supports half-duplex only operations and can

interface to a single 24-bit data bus (two parallel 12-bit buses).

Both the U12 and L12 buses are used on the AD9863. The logic

level of the Tx/Rx selector (controlled through IFACE1 pin) is

used to configure the buses as Rx outputs (during Rx operation)

or as Tx inputs (during Tx operation). A single pin is used to

output the clocks for Rx and Tx data latching (from the IFACE3

pin) switching, depending on which path is enabled.

The following notes provide a general description of the HD24

mode configuration. For more information, refer to Table 15.

Note the following about the Tx path in HD24 mode:

•

Interpolation rate of 1×, 2×, or 4× can be programmed

with mode pins or SPI.

•

Max DAC update rate = 200 MSPS.

Max Tx input data rate = 160 MSPS/channel with bypassed

interpolation filters, 100 MSPS for 2× interpolation, or

50 MSPS for 4× interpolation.

•

Tx_A DAC data is accepted from the U12 bus; Tx_B DAC

data is accepted from the L12 bus.

Note the following about the Rx path in HD24 mode:

•

ADC CLK Div register can be used to divide down the

clock driving the ADC, which accepts up to 50 MHz.

•

Max ADC sampling rate = 50 MSPS.

•

The Rx_A output data is output on L12 bus; the Rx_B

output data is output on U12 bus.

Clone Mode

Clone mode is an interface mode that provides a similar

interface to the AD9860 when used in half-duplex mode. This

mode requires SPI to configure.

Clone mode provides a parallel Rx data output (24 bits) while in

Rx mode, and it accepts interleaved Tx data (12-bit) while in Tx

mode. Both the U12 and L12 buses are used on the AD9863.

The logic level of the Tx/Rx selector (controlled through the

IFACE1 pin) is used to configure the buses for Rx outputs

(during Rx operation) or as Tx inputs (during Tx operation). A

single pin is used to output the clocks for Rx and Tx data

latching (from the IFACE3 pin), depending on which path is

enabled. Clone mode requires interpolation of 2× or 4×.

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