AD9863

Rev. A| Page 24 of 40

Table 11 describes AD9863 pin function (when mode pins are used) relative to I/O mode and for half-duplex modes, whether

transmitting or receiving.

Table 11. AD9863 Pin Function vs. Interface Mode (No SPI Cases)1

Mode Name

U12 Bus

L12 Bus

IFACE1

IFACE2

IFACE3

FD

Interleaved Tx data

Interleaved Rx data

TxSYNC

Buffered Rx Clock

Buffered Tx clock

HD12

(Tx/Rx = High)

Interleaved Tx data

MSB = TxSYNC

Others = three-state

Tx/Rx = tied high

12/24 pin control tied high

Buffered Tx clock

HD12

(Tx/Rx = Low)

MSB = RxSYNC

Others = three-state

Interleaved Rx data

Tx/Rx = tied low

12/24 pin control tied high

Buffered Rx clock

HD24

(Tx/Rx = High)

Tx_A data

Tx_B data

Tx/Rx = tied high

12/24 pin control tied low

Buffered Tx clock

HD24

(Tx/Rx = Low)

Rx_B data

Rx_A data

Tx/Rx = tied low

12/24 pin control tied low

Buffered Rx clock

Clone Mode

(Tx/Rx = High)

x

x

x

x

x

Clone Mode

(Tx/Rx = Low)

x

x

x

x

x

Table 12 describes AD9863 pin function (when SPI programming is used) relative to flexible I/O mode and for half-duplex modes,

whether transmitting or receiving.

Table 12. AD9863 Pin Function vs. Interface Mode (Configured through the SPI Registers)

Mode Name

U12 Bus

L12 Bus

IFACE1

IFACE2

IFACE3

FD

Interleaved Tx data

Interleaved Rx data

TxSYNC

Buffered system

clock

Buffered Tx clock

HD12, Tx Mode

(Tx/Rx = High)

Interleaved Tx data

MSB = TxSYNC

others = three-state

Tx/Rx = tied high

Optional buffered

system clock

Buffered Tx clock

HD12, Rx Mode

(Tx/Rx = Low)

MSB = RxSYNC

Other = three-state

Interleaved Tx data

Tx/Rx = tied low

Optional buffered

system clock

Buffered Rx clock

HD24, Tx Mode

(Tx/Rx = High)

Tx_A data

Tx_B data

Tx/Rx = tied high

Optional buffered

system clock

Buffered Tx clock

HD24, Rx Mode

(Tx/Rx = Low)

Rx_B data

Rx_A data

Tx/Rx = tied low

Optional buffered

system clock

Buffered Rx clock

Clone Mode,

Tx Mode

(Tx/Rx = High)

Interleaved Tx data

MSB = TxSYNC

Others = three-state

Tx/Rx = tied high

Optional buffered

system clock

Buffered Tx clock

Clone Mode,

Rx Mode

(Tx/Rx = Low)

Rx_B data

Rx_A data

Tx/Rx = tied low

Optional buffered

system clock

Buffered Rx clock

Summary of Flexible I/O Modes

FD Mode

The full-duplex (FD) mode can be configured by using mode

pins or with SPI programming. Using the SPI allows additional

configuration flexibility of the device.

FD mode is the only mode that supports full-duplex, receive,

and transmit concurrent operations. The upper 12-bit bus

(U12) is used to accept interleaved Tx data, and the lower 12-bit

bus (L12) is used to output interleaved Rx data. Either the Rx

path or the Tx path (or both) can be independently powered

down using either (or both) the RxPwrDwn and TxPwrDwn

pins. FD mode requires interpolation of 2× or 4×.

The following notes provide a general description of the FD

mode configuration. For more information, refer to Table 15.

Note the following about the Tx path in FD mode:

•

Interpolation rate of 2× or 4× can be programmed with

mode pins or SPI.

•

Max DAC update rate = 200 MSPS.

Max Tx input data rate = 80 MSPS/channel (160 MSPS

interleaved).

•

TxSYNC is used to direct Tx input data.

TxSYNC = high indicates channel Tx_A data.

TxSYNC = low indicates channel Tx_B data.