AD9863 datasheet(36/40 Pages) AD

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AD9863

Rev. A| Page 36 of 40

CLOCK DISTRIBUTION BLOCK

Theory/Description

The AD9863 uses a PLL clock multiplier circuit and an internal

distribution block to generate all required clocks for various

timing configurations. The AD9863 has two independent input

clocks, CLKIN1 and CLKIN2. The CLKIN1 is primarily used to

drive the Rx ADCs path. The CLKIN2 is primarily used to drive

the TxDACs path. There are many options for configuring the

clock distribution block, which are programmed through

internal register settings. The Clock Distribution Block Diagram

section describes the timing block diagram breakdown, followed

by the data timing for the different data interface options.

The clock distribution block contains a PLL, which includes an

optional output divide-by-5 circuit, an ADC divide-by-2 circuit,

multiplexers, and other digital logic.

There are two main methods of configuring the Rx path timing

of the AD9863: normal timing mode and alternate timing

mode, which are controlled through Register 0x15, Bit 4. In

normal timing mode, the Rx path clock is driven directly from

the CLKIN1 input, and the Tx path is driven by a clock derived

from CLKIN2 multiplied by the on-chip PLL. In alternative

timing mode, the CLKIN2 drives the PLL circuitry, and the PLL

output clock drives both the Rx path clock and Tx path clock.

Because alternate timing mode uses the PLL to derive the Rx

path clock, the ADC performance may degrade slightly. This

degradation is due to the phase noise from the PLL, although

typically it is only noticeable in undersampling applications

when the input signal is above the first Nyquist zone of the ADC.

The PLL can provide 1×, 2×, 4×, 8×, and 16× multiplication or

can be bypassed and powered down through register PLL

bypass [Register 0x15, Bit 7] and through register PLL power-

down [Register 0x02, Bit 2]. The PLL requires a minimum input

clock frequency of 16 MHz and needs to provide a minimum

PLL output clock of 32 MHz. This limit applies to the PLL

output prior to the optional divide-by-5 circuitry. For clock

frequencies below these limits, the PLL must be bypassed. The

PLL maximum output frequency before the divide-by-5 circuitry

is 350 MHz. Table 20 shows the input and output clock rates for

all the multiplication settings.

Table 20. PLL Input and Output Minimum and Maximum

Clock Rates

PLL Setting

CLKIN2 Input

(Min/Max) (MHz)

PLL Output Clock

(Min/Max) (MHz)

1× (PLL Bypassed)

1 /200

1× (PLL Enabled)

32 /200

2×

16 /100

32 /200

4×

16 /50

64 /200

8×

16 /25

128 /200

1/5 ×1

32 /200

6.4 /40

2/5 ×1

16 /175

6.4 /70

4/5 ×1

16 /87.5

12.8 /70

8/5 ×1

16 /43.75

25.6 /70

16/5 ×1

16 /21.875

51.2 /70

1 Indicates PLL output divide-by-5 circuit enabled.

Clock Distribution Block Diagram

The clock distribution block diagram is shown in

Figure 58. An output clock formatter configures the output

synchronization signals, IFACE1, IFACE2, and IFACE3. These

interface pin signals depend on clock mode setting, data I/O

configuration, and other operational settings. Clock mode and

data I/O configuration are defined in register settings of

clk_mode, SpiFD/HD, and SpiB12/24.

Table 21 shows the configuration of the IFACE1, IFACE2, and

IFACE3 pins relative to clock mode. For half-duplex cases, the

IFACE1 pin is an input that identifies if the device is in Rx or Tx

operation mode. The clock mode is used to specify the timing

for each data interface operation mode, presented in detail in

the Flexible I/O Interface Options section. The T and R

extensions after half-duplex Modes 4 and 5, Modes 7 and 8, and

Mode 10 in Table 21 indicate that the device is in transmit or

receive operation mode. The default clock mode setting

[Register 0x01, Bit 5 to Bit 7, Clk_Mode] of 000 configures

clock Mode 1 for the full-duplex operation, Mode 4 for half-

duplex 24 operation, and Mode 7 for half-duplex 12 operation.

Mode 2, Mode 5, Mode 8, and Mode 10 are optional timing

configurations for the AD9863 and can be programmed

through Register 0x01 Clk_Mode.

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