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AD9863 Datasheet(PDF) 28 Page - Analog Devices |
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AD9863 Datasheet(HTML) 28 Page - Analog Devices |
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28 / 40 page ![]() AD9863 Rev. A| Page 28 of 40 Configuring with SPI The flexible interface can be configured with register settings. Using the register allows more device programmability. Table 15 shows the required register writes to configure the AD9863 for FD, optional FD, HD24, optional HD24, HD12, optional HD12, and clone modes. Note that for modes that use interleaved data buses, enabling 2× or 4× interpolation is required. Table 15. Registers for Configuring SPI Register Address Setting Description FD, Mode 1 Register 0x01 [7:5] [000] Clk_Mode. Configures timing mode. Register 0x14 [4] High SPIFD/HD. Configures FD mode. Register 0x14 [2] High SpiB12/24. Configures FD mode. Register 0x13 [1:0] [01] or [10] Interpolation Control. Configures 2× or 4× interpolation. Optional FD, Mode 2 Register 0x01 [7:5] [001] Clk_Mode. Configures timing mode. Register 0x14 [4] High SPIFD/HD. Configures FD mode. Register 0x14 [2] High SpiB12/24. Configures FD mode. Register 0x13 [1:0] [01] or [10] Interpolation Control. Configures 2× or 4× interpolation. HD24, Mode 4 Register 0x01 [7:5] [000] Clk_Mode. Configures timing mode. Register 0x14 [4] Low SPIFD/HD. Configures HD mode. Register 0x14 [2] Low SpiB12/24. Configures HD24 mode. Register 0x13 [1:0] [00], [01], or [10] Interpolation Control. Configures 1×, 2×, or 4× interpolation. Optional HD24, Mode 5 Register 0x01 [7:5] [011] Clk_Mode. Configures timing mode. Register 0x14 [4] Low SPIFD/HD. Configures HD mode. Register 0x14 [2] Low SpiB12/24. Configures HD24 mode. Register 0x13 [1:0] [00], [01], or [10] Interpolation Control. Configures 1×, 2×, or 4× interpolation. HD12, Mode 7 Register 0x01 [7:5] [000] Clk_Mode. Configures timing mode. Register 0x14 [4] Low SPIFD/HD. Configures HD mode. Register 0x14 [2] High SpiB12/24. Configures HD12 mode. Register 0x13 [1:0] [01] or [10] Interpolation Control. Configures 2× or 4× interpolation. Optional HD12, Mode 8 Register 0x01 [7:5] [101] Clk_Mode. Configures timing mode. Register 0x14 [4] Low SPIFD/HD. Configures HD mode. Register 0x14 [2] High SpiB12/24. Configures HD12 mode. Register 0x13 [1:0] [01] or [10] Interpolation Control. Configures 2× or 4× interpolation. Clone, Mode 10 Register 0x01 [7:5] [111] Clk_Mode. Configures timing mode. Register 0x14 [0] High SpiClone. Configures clone mode. Register 0x13 [1:0] [01] or [10] Interpolation Control. Configures 2× or 4× interpolation. |
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