AD9863 datasheet(19/40 Pages) AD

19 / 40 page

AD9863

Rev. A | Page 19 of 40

Rx Path Application Section

Adding series resistance between the output of the signal source

and the VIN pins reduces the drive requirements placed on the

signal source. Figure 47 shows this configuration.

RSERIES

VIN+

CSHUNT

AD9863

VIN–

Figure 47. Typical Input

The bandwidth of the particular application limits the size of

this resistor. For applications with signal bandwidths less than

10 MHz, the user may insert series input resistors and a shunt

capacitor to produce a low-pass filter for the input signal. In

addition, adding a shunt capacitance between the VIN pins

can lower the ac load impedance. The value of this capaci

tance depends on the source resistance and the required

signal bandwidth.

The Rx input pins are self-biased to provide this midsupply,

common-mode bias voltage, so it is recommended to ac couple

the signal to the inputs using dc blocking capacitors. In systems

that must use dc coupling, use an op amp to comply with the

input requirements of the AD9863. The inputs accept a signal

with a 2 V p-p differential input swing centered about one-half

of the supply voltage (AVDD/2). If the dc bias is supplied exter-

nally, the internal input bias circuit should be powered down by

writing to registers Rx_A dc bias [Register 0x03, Bit 6] and

Rx_B dc bias [Register 0x04, Bit 7].

The ADCs in the AD9863 are designed to sample differential

input signals. The differential input provides improved noise

immunity and better THD and SFDR performance for the Rx

path. In systems that use single-ended signals, these inputs can

be digitized, but it is recommended that a single-ended-to-

differential conversion be performed. A single-ended-to-

differential conversion can be performed by using a transformer

coupling circuit (typically for signals above 10 MHz) or by

using an operational amplifier, such as the AD8138 (typically

for signals below 10 MHz).

ADC Voltage References

The AD9863 12-bit ADCs use internal references that are

designed to provide for a 2 V p-p differential input range. The

internal band gap reference generates a stable 1 V reference

level and is decoupled through the VREF pin. REFT and REFB

are the differential references generated based on the voltage

level of VREF. Figure 48 shows the proper decoupling of the

reference pins VREF, REFT, and REFB when using the internal

reference. Decoupling capacitors should be placed as close to

the reference pins as possible.

External references REFT and REFB are centered at AVDD/2

with a differential voltage equal to the voltage at VREF (by

default 1 V when using the internal reference), allowing a peak-

to-peak differential voltage swing of 2× VREF. For example, the

default 1 V VREF reference accepts a 2 V p-p differential input

swing, and the offset voltage should be

REFT = AVDD/2 + 0.5 V

REFB = AVDD/2 − 0.5 V

0.1

µF

0.1

µF

0.1

µF

0.1

µF

VREF

AD9863

0.5V

TO ADCs

REFT

REFB

µF

Figure 48. Typical Rx Path Decoupling

An external reference may be used for systems that require a

different input voltage range, high accuracy gain matching

between multiple devices, or improvements in temperature drift

and noise characteristics. When an external reference is desired,

the internal Rx band gap reference must be powered down

using the VREF register [Register 0x05, Bit 4], with the external

reference driving the voltage level on the VREF pin. The exter-

nal voltage level should be one-half of the desired peak-to-peak

differential voltage swing. The result is that the differential

voltage references are driven to new voltages:

REFT = AVDD/2 +VREF/2 V

REFB = AVDD/2 − VREF/2 V

If an external reference is used, it is recommended not to exceed

a differential offset voltage greater than 1 V for the reference.

Clock Input and Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals and, as a result, may be sensi-

tive to clock duty cycle. Commonly, a 5% tolerance is required

on the clock duty cycle to maintain dynamic performance

characteristics. The AD9863 contains clock duty cycle stabilizer

circuitry (DCS). The DCS retimes the internal ADC clock

(nonsampling edge) and provides the ADC with a nominal 50%

duty cycle. Input clock rates of over 40 MHz can use the DCS so

that a wide range of input clock duty cycles can be

accommodated. Conversely, DCS should not be used for Rx

sampling below 40 MSPS. Maintaining a 50% duty cycle clock is

particularly important in high speed applications when proper

sample-and-hold times for the converter are required to

maintain high performance. The DCS can be enabled by

writing highs to the Rx_A/Rx_B CLK duty register bits

[Register 0x06/Register 0x07, Bit 4].

The duty cycle stabilizer uses a delay-locked loop to create the

nonsampling edge. As a result, any changes to the sampling

frequency require approximately 2 µs to 3 µs to allow the DLL

to adjust to the new rate and settle. High speed, high resolution

ADCs are sensitive to the quality of the clock input. The

AD9863 Datasheet(PDF) 19 Page - Analog Devices

AD9863 Datasheet(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL