AD9863 datasheet(33/40 Pages) AD

33 / 40 page

AD9863

Rev. A | Page 33 of 40

PROGRAMMABLE REGISTERS

The AD9863 contains internal registers that are used to configure

the device. A serial port interface provides read/write access to

the internal registers. Single-byte or dual-byte transfers are

supported, as well as MSB first or LSB first transfer formats. The

AD9863’s serial interface port can be configured as a single pin

I/O (SDIO) or as two unidirectional pins for in/out (SDIO/SDO).

The serial port is a flexible, serial communications port, allowing

easy interface to many industry-standard microcontrollers and

microprocessors.

General Operation of the Serial Interface

By default, the serial port accepts data in MSB first mode and

uses four pins: SEN, SCLK, SDIO, and SDO, by default. SEN is a

serial clock enable pin; SCLK is the serial clock pin; SDIO is a

bidirectional data line; and SDO is a serial output pin.

SEN is an active low control gating read and write cycles. When

SEN is high, SDO and SDIO go into a high impedance state.

SCLK is used to synchronize SPI reads and writes at a

maximum bit rate of 30 MHz. Input data is registered on the

rising edge, and output data transitions are registered on the

falling edge. During write operations, the registers are updated

after the 16th rising clock edge (and 24th rising clock edge for

the dual-byte case). Incomplete write operations are ignored.

SDIO is an input data only pin by default. Optionally, a 3-pin

interface may be configured using the SDIO for both input and

output operations and three-stating the SDO pin. Refer to the

SDIO BiDir bit in Register 0x00 shown in Table 17.

SDO is a serial output data pin used for readback operations in

4-wire mode and is three-stated when SDIO is configured for

bidirectional operation.

There are two phases to a communication cycle with the AD9863.

Phase 1 is the instruction cycle, which is the writing of an

instruction byte into the AD9863, coincident with the first eight

SCLK rising edges. The instruction byte provides the AD9863

serial port controller with information regarding the data

transfer cycle, which is Phase 2 of the communication cycle.

The Phase 1 instruction byte defines whether the upcoming

data transfer is read or write, the number of bytes in the data

transfer (one or two), and the starting register address for the

first byte of the data transfer.

The first eight SCLK rising edges of each communication cycle

are used to write the instruction byte into the AD9863. The

remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the AD9863

and the system controller. Phase 2 of the communication cycle

is a transfer of one or two data bytes as determined by the

instruction byte. Normally, using one communication cycle in a

multibyte transfer is the preferred method; however, single byte

communication cycles are useful to reduce CPU overhead when

write the AD9863 power-down bits.

All data input to the AD9863 is registered on the rising edge of

SCLK. All data is driven out of the AD9863 on the falling edge

of SCLK.

Instruction Byte

The instruction byte contains the information shown in

Table 18, and the bits are described in detail after the table.

Table 18. Instruction Byte

MSB

LSB

R/W

2/1

Byte

R/W—Bit 7 of the instruction byte determines whether a read

or write data transfer will occur after the instruction byte write.

Logic high indicates a read operation. Logic low indicates a

write operation.

2/1 Byte

—Bit 6 of the instruction byte determines the number

of bytes to be transferred during the data transfer cycle of the

communication cycle. Logic high indicates a 2-byte transfer.

Logic low indicates a 1-byte transfer.

A5, A4, A3, A2, A1, A0

—Bit 5 to Bit 0 of the instruction byte

determine which register is accessed during the data transfer

portion of the communication cycle. For 2-byte transfers, this

address is the starting byte address. The second byte address is

automatically decremented when the interface is configured for

MSB-first transfers. For LSB-first transfers, the address of the

second byte is automatically incremented.

Table 19. Serial Port Interface Timing

Maximum SCLK Frequency (fSCLK)

40 MHz

Minimum SCLK High Pulse Width (tPWH)

12.5 ns

Minimum SCLK Low Pulse Width (tPWL)

12.5 ns

Maximum Clock Rise/Fall Time

1 ms

Data to SCLK timing (tDS)

12.5 ns

Data Hold Time (tDH)

0 ns

AD9863 Datasheet(PDF) 33 Page - Analog Devices

AD9863 Datasheet(HTML) 33 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL