AD9863 datasheet(26/40 Pages) AD

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AD9863

Rev. A| Page 26 of 40

The following notes provide a general description of the clone

mode configuration. For more information, refer to Table 15.

Note the following about the Tx path in clone mode:

•

Interpolation rate of 2× or 4× can be programmed with

mode pins or SPI.

•

Max DAC update rate = 200 MSPS.

Max Tx input data rate = 80 MSPS/channel (160 MSPS

interleaved).

•

TxSYNC is used to direct Tx input data.

TxSYNC = high indicates channel Tx_A data.

TxSYNC = low indicates channel Tx_B data.

•

Buffered Tx clock output (from IFACE3 pin) uses one

rising edge per interleaved Tx sample.

Note the following about the Rx path in clone mode:

•

ADC CLK Div register can be used to divide down the

clock driving the ADC, which accepts up to 50 MHz.

•

Max ADC sampling rate = 50 MSPS.

•

Output data rate = ADC sample rate, that is, two 12-bit

parallel outputs per one buffer Rx clock output cycle.

•

The Rx_A output data is output on L12 bus; the Rx_B

output data is output on U12 bus.

Configuring with Mode Pins

The flexible interface can be configured with or without the

SPI, although more options and flexibility are available when

using the SPI to program the AD9863. Mode pins can be used

to power down sections of the device, reduce overall power

consumption, configure the flexible I/O interface, and

program the interpolation setting. The SPI register map,

which provides many more options, is presented in the

Configuring with SPI section.

Mode Pins/Power-Up Configuration Options

Mode pins provide various options that are configurable at

power-up. Control pins also provide options for power-down

modes. The logic value of the configuration mode pins are

latched when the device is brought out of reset (upon the rising

edge of RESET). The mode pin names and functions are listed

in Table 13. Table 14 provides a detailed description of the

mode pins.

Table 13. Mode Pin Names and Functions

Pin Name

Duration

Function

RxPWRDWN

Permanent

When high, digital clocks to the Rx block are disabled. Analog circuitry that requires <10 µs

to power up is powered off.

TxPWRDWN

Permanent

When high, digital clocks to Tx block are disabled (PLL remains powered). Analog circuitry

that requires <10 µs to power up is powered off.

Tx/Rx (IFACE1)

Permanent only for

HD Flex I/O interface

When high, digital clocks to the Tx block are disabled (PLL remains powered to maintain

output clock with an optional SPI shutoff). Tx analog circuitry remains powered up unless

Tx_PwrDwn is asserted.

When low, digital clocks to Rx block are disabled. Rx analog circuitry remains powered up

unless Rx_PwrDwn is asserted.

ADC_LO_PWR

Defined at reset or

power-up

When enabled, this bit scales the ADC power-down by 40%.

SPI_Bus_Enable

(SPI_CS)

Defined at reset or

power-up

This function is controlled through the SPI_CS pin. This pin must remain low to maintain

mode pin functionality (the SPI port remains nonfunctional). This pin must be high when

coming out of reset to enable the SPI.

FD/HD

Defined at reset or

power-up

Configures the flex I/O for FD or HD mode. This control applies only if the SPI bus is disabled.

12/24

Only valid for HD

mode

Defined at reset or

power-up

If the flex I/O bus is in HD mode, this bit is used to configure parallel or interleaved data

mode. This control applies only if the SPI bus is disabled.

Interp0 and

Interp1

Defined at reset or

power-up

The Interp1 and Interp0 bits configure the PLL and the interpolation rate to 1× [00], 2× [01],

or 4× [10]. This control applies only if the SPI bus is disabled.

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