AD9863 datasheet(22/40 Pages) AD

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AD9863

Rev. A| Page 22 of 40

channels and aiding in suppressing LO feedthrough. This is

especially useful in image rejection architectures. The 10-bit dc

offset control of each DAC can be used independently to pro-

vide an offset of up to ±12% of IOUTFSMAX to either differential

pin, thus allowing calibration of any system offset. The fine gain

control with 5-bit resolution allows the IOUTFSMAX of each DAC to

be varied over a ±4% range, allowing compensation of any DAC

or system gain mismatches. Fine gain control is set through the

DAC A/DAC B fine gain registers, and the offset control of each

DAC is accomplished using the DAC A/DAC B offset registers.

Clock Input Configuration

The quality of the clock and data input signals is important

in achieving optimum performance. The external clock driver

circuitry provides the AD9863 with a low jitter clock input

that meets the min/max logic levels while providing fast

edges. When a driver is used to buffer the clock input, it

should be placed very close to the AD9863 clock input,

thereby negating any transmission line effects such as

reflections due to mismatch.

Programmable PLL

CLKIN2 can function either as an input data rate clock (PLL

enabled) or as a DAC data rate clock (PLL disabled).

The PLL clock multiplier and distribution circuitry produce the

necessary internal timing to synchronize the rising edge trig-

gered latches for the enabled interpolation filters and DACs.

This circuitry consists of a phase detector, charge pump, voltage

controlled oscillator (VCO), and clock distribution block, all

under SPI port control. The charge pump, phase detector, and

VCO are powered from PLL_AVDD, while the clock distribu-

tion circuits are powered from the DVDD supply.

To ensure optimum phase noise performance from the PLL

clock multiplier circuits, PLL_AVDD should originate from a

clean analog supply. The speed of the VCO within the PLL also

has an effect on phase noise.

The PLL locks with VCO speeds as low as 32 MHz up to

350 MHz, but optimal phase noise with respect to VCO speed is

achieved by running it in the range of 64 MHz to 200 MHz.

Power Dissipation

The AD9863 Tx path power is derived from three voltage supplies:

AVDD, DVDD, and DRVDD.

IDRVDD and IDVDD are very dependent on the input data

rate, the interpolation rate, and the activation of the internal

digital modulator. IAVDD has the same type of sensitivity to

data, interpolation rate, and the modulator function, but to a

much lesser degree (<10%).

Sleep/Power-Down Modes

The AD9863 provides multiple methods for programming power

saving modes. The externally controlled TxPWRDWN or SPI

programmed sleep mode and the full power-down mode are the

main options.

TxPWRDWN is used to disable all clocks and much of the analog

circuitry in the Tx path when asserted. In this mode, the biases

remain active, therefore reducing the time required for re-enabling

the Tx path. The time of recovery from power-down for this mode

is typically less than 10 µs.

Sleep mode, when activated, turns off the DAC output currents, but

the rest of the chip remains functioning. When coming out of sleep

mode, the AD9863 immediately returns to full operation.

A full power-down mode can be enabled through the SPI register,

which turns off all Tx path related analog and digital circuitry in

the AD9863. When returning from full power-down mode,

enough clock cycles must be allowed to flush the digital filters of

random data acquired during the power-down cycle.

Interpolation Stage

Interpolation filters are available for use in the AD9863 transmit

path, providing 1× (bypassed), 2×, or 4× interpolation.

The interpolation filters effectively increase the Tx data rate while

suppressing the original images. The interpolation filters digitally

shift the worst-case image further away from the desired signal,

thus reducing the requirements on the analog output

reconstruction filter.

There are two 2× interpolation filters available in the Tx path. An

interpolation rate of 4× is achieved using both interpolation filters;

an interpolation rate of 2× is achieved by enabling only the first 2×

interpolation filter.

The first interpolation filter provides 2× interpolation using a

39-tap filter. It suppresses out-of-band signals by 60 dB or more

and has a flat pass-band response (less than 0.1 dB ripple)

extending to 38% of the input Tx data rate (19% of the DAC update

rate, fDAC). The maximum input data rate is 80 MSPS per channel

when using 2× interpolation.

The second interpolation filter provides an additional 2× interpola-

tion for an overall 4× interpolation. The second filter is a 15-tap

filter, which suppresses out-of-band signals by 60 dB or more.

The flat pass-band response (less than 0.1 dB attenuation) is 38% of

the Tx input data rate (9.5% of fDAC). The maximum input data rate

per channel is 50 MSPS per channel when using 4× interpolation.

Latch/Demultiplexer

Data for the dual-channel Tx path can be latched in parallel

through two ports in half-duplex operations (HD24 mode) or

through a single port by interleaving the data (FD, HD12, and

clone modes). See the Flexible I/O Interface Options section in the

Digital Block description that follows and the Clock Distribution

Block section for further descriptions of each mode.

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